Searched +full:hix5hd2 +full:- +full:clock (Results 1 – 14 of 14) sorted by relevance
1 * Hisilicon Hix5hd2 Clock Controller3 The hix5hd2 clock controller generates and supplies clock to various4 controllers within the hix5hd2 SoC.8 - compatible: should be "hisilicon,hix5hd2-clock"9 - reg: Address and length of the register set10 - #clock-cells: Should be <1>12 Each clock is assigned an identifier and client nodes use this identifier13 to specify the clock which they consume.15 All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.18 clock: clock@f8a22000 {[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2013-2014 Linaro Ltd.4 * Copyright (c) 2013-2014 Hisilicon Limited.7 #include <dt-bindings/clock/hix5hd2-clock.h>10 #address-cells = <1>;11 #size-cells = <1>;17 gic: interrupt-controller@f8a01000 {18 compatible = "arm,cortex-a9-gic";19 #interrupt-cells = <3>;20 #address-cells = <0>;[all …]
4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.7 * SPDX-License-Identifier: GPL-2.010 #include <dt-bindings/clock/histb-clock.h>11 #include <dt-bindings/interrupt-controller/arm-gic.h>12 #include <dt-bindings/reset/ti-syscon.h>16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;21 compatible = "arm,psci-0.2";26 #address-cells = <2>;[all …]
1 I2C for Hisilicon hix5hd2 chipset platform4 - compatible: Must be "hisilicon,hix5hd2-i2c"5 - reg: physical base address of the controller and length of memory mapped7 - interrupts: interrupt number to the cpu.8 - #address-cells = <1>;9 - #size-cells = <0>;10 - clocks: phandles to input clocks.13 - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 10000014 - Child nodes conforming to i2c bus binding18 compatible = "hisilicon,hix5hd2-i2c";[all …]
1 Device-Tree bindings for hix5hd2 ir IP4 - compatible: Should contain "hisilicon,hix5hd2-ir", or:5 - "hisilicon,hi3796cv300-ir" for Hi3796CV300 IR device.6 - reg: Base physical address of the controller and length of memory8 - interrupts: interrupt-specifier for the sole interrupt generated by11 - clocks: clock phandle and specifier pair.14 - linux,rc-map-name: see rc.txt file in the same directory.15 - hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files.21 compatible = "hisilicon,hix5hd2-ir";24 clocks = <&clock HIX5HD2_IR_CLOCK>;[all …]
1 Hisilicon hix5hd2 gmac controller4 - compatible: should contain one of the following SoC strings:5 * "hisilicon,hix5hd2-gmac"6 * "hisilicon,hi3798cv200-gmac"7 * "hisilicon,hi3516a-gmac"9 * "hisilicon,hisi-gmac-v1"10 * "hisilicon,hisi-gmac-v2"11 The version v1 includes SoCs hix5hd2.13 - reg: specifies base physical address(s) and size of the device registers.16 - interrupts: should contain the MAC interrupt.[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Wei Xu <xuwei5@hisilicon.com>13 The clock registers and power registers of secondary cores are defined14 in CPU controller, especially in HIX5HD2 SoC.19 - const: hisilicon,cpuctrl24 "#address-cells":27 "#size-cells":33 - compatible[all …]
1 // SPDX-License-Identifier: GPL-2.0-only14 #include <media/rc-core.h>62 #define IR_HIX5HD2_NAME "hix5hd2-ir"87 struct clk *clock; member94 u32 clk_reg = dev->socdata->clk_reg; in hix5hd2_ir_clk_enable()98 if (dev->regmap) { in hix5hd2_ir_clk_enable()99 regmap_read(dev->regmap, clk_reg, &val); in hix5hd2_ir_clk_enable()107 regmap_write(dev->regmap, clk_reg, val); in hix5hd2_ir_clk_enable()110 ret = clk_prepare_enable(dev->clock); in hix5hd2_ir_clk_enable()112 clk_disable_unprepare(dev->clock); in hix5hd2_ir_clk_enable()[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.8 #include <dt-bindings/clock/histb-clock.h>9 #include <dt-bindings/gpio/gpio.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/phy/phy.h>12 #include <dt-bindings/reset/ti-syscon.h>16 interrupt-parent = <&gic>;17 #address-cells = <2>;18 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later72 HIX5I2C_STAT_RW_ERR = -1,97 u32 val = readl_relaxed(priv->regs + HIX5I2C_SR); in hix5hd2_i2c_clr_pend_irq()99 writel_relaxed(val, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_pend_irq()106 writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_all_irq()111 writel_relaxed(0, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_disable_irq()117 priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_enable_irq()126 val = readl_relaxed(priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()127 writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()129 rate = priv->freq; in hix5hd2_i2c_drv_setrate()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only18 controller is part of the 7101 device, which is an ACPI-compliant22 will be called i2c-ali1535.30 controller is part of the 7101 device, which is an ACPI-compliant34 will be called i2c-ali1563.44 will be called i2c-ali15x3.56 will be called i2c-amd756.63 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed69 will be called i2c-amd756-s4882.79 will be called i2c-amd8111.[all …]
1 # SPDX-License-Identifier: GPL-2.03 # Hisilicon Clock specific Makefile6 obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o8 obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o9 obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o10 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o11 obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o12 obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o13 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o14 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only8 #include <dt-bindings/clock/hix5hd2-clock.h>174 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()175 val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; in clk_ether_prepare()176 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()177 val &= ~(clk->ctrl_rst_mask); in clk_ether_prepare()178 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()180 val = readl_relaxed(clk->phy_reg); in clk_ether_prepare()181 val |= clk->phy_clk_mask; in clk_ether_prepare()182 val &= ~(clk->phy_rst_mask); in clk_ether_prepare()[all …]
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