Searched +full:hi6220 +full:- +full:sysctrl (Results 1 – 8 of 8) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Wei Xu <xuwei5@hisilicon.com>17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the23 Hisilicon system controller --> hisilicon,sysctrl24 HiP01 system controller --> hisilicon,hip01-sysctrl25 Hi6220 system controller --> hisilicon,hi6220-sysctrl26 Hi3519 system controller --> hisilicon,hi3519-sysctrl[all …]
1 * Hisilicon Hi6220 Clock Controller3 Clock control registers reside in different Hi6220 system controllers,11 - compatible: the compatible should be one of the following strings to14 - "hisilicon,hi6220-acpu-sctrl"15 - "hisilicon,hi6220-aoctrl"16 - "hisilicon,hi6220-sysctrl"17 - "hisilicon,hi6220-mediactrl"18 - "hisilicon,hi6220-pmctrl"19 - "hisilicon,hi6220-stub-clk"21 - reg: physical base address of the controller and length of memory mapped[all …]
7 The reset controller registers are part of the system-ctl block on8 hi6220 SoC.11 - compatible: should be one of the following:12 - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.13 - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.14 - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.15 - reg: should be register base and length as documented in the17 - #reset-cells: 1, see below21 compatible = "hisilicon,hi6220-sysctrl", "syscon";23 #clock-cells = <1>;[all …]
2 * dts file for Hisilicon Hi6220 SoC7 #include <dt-bindings/interrupt-controller/arm-gic.h>8 #include <dt-bindings/clock/hi6220-clock.h>11 compatible = "hisilicon,hi6220";12 interrupt-parent = <&gic>;13 #address-cells = <2>;14 #size-cells = <2>;17 compatible = "arm,psci-0.2";22 #address-cells = <2>;23 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Hisilicon Hi6220 reset controller driver6 * Copyright (c) 2015-2016 Hisilicon Limited.19 #include <linux/reset-controller.h>48 struct regmap *regmap = data->regmap; in hi6220_peripheral_assert()60 struct regmap *regmap = data->regmap; in hi6220_peripheral_deassert()77 struct regmap *regmap = data->regmap; in hi6220_media_assert()86 struct regmap *regmap = data->regmap; in hi6220_media_deassert()110 struct regmap *regmap = data->regmap; in hi6220_ao_assert()129 struct regmap *regmap = data->regmap; in hi6220_ao_deassert()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Hisilicon Hi6220 clock driver11 #include <linux/clk-provider.h>19 #include <dt-bindings/clock/hi6220-clock.h>90 CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);93 /* clocks in sysctrl */197 CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);254 CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);285 CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);307 CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init);
1 // SPDX-License-Identifier: GPL-2.03 * dts file for Hisilicon Hi6220 SoC8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/reset/hisi,hi6220-resets.h>10 #include <dt-bindings/clock/hi6220-clock.h>11 #include <dt-bindings/pinctrl/hisi.h>12 #include <dt-bindings/thermal/thermal.h>15 compatible = "hisilicon,hi6220";16 interrupt-parent = <&gic>;17 #address-cells = <2>;[all …]
... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...