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/rk3399_rockchip-uboot/tools/buildman/
H A DREADME3 # SPDX-License-Identifier: GPL-2.0+
8 Quick-start
14 cd /path/to/u-boot
16 buildman --fetch-arch arm
17 buildman -k rpi_2
19 # u-boot.bin is the output image
25 This tool handles building U-Boot to check that you have not broken it
28 to make full use of multi-processor machines.
40 where it left off. This should happen cleanly and without side-effects.
44 You may need to press Ctrl-C several times to quit it. Also it will print
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/rk3399_rockchip-uboot/doc/uImage.FIT/
H A Dbeaglebone_vboot.txt5 ------------
7 Before reading this, please read verified-boot.txt and signature.txt. These
8 instructions are for mainline U-Boot from v2014.07 onwards.
11 verified boot works in U-Boot. There is also a test which runs through the
12 entire process of signing an image and running U-Boot (sandbox) to check it.
16 for an example of how to enable verified boot using U-Boot.
18 First a note that may to help avoid confusion. U-Boot and Linux both use
21 U-Boot has its device tree packaged wtih it, and the kernel's device tree is
23 since U-Boot's device tree must be immutable. If it can be changed then the
25 simply generate a new key and put his public key into U-Boot so that
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/rk3399_rockchip-uboot/arch/arm/
H A DKconfig14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
20 information that is embedded into the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
47 # If set, the workarounds for these ARM errata are applied early during U-Boot
49 # applied; no CPU-type/version detection exists, unlike the similar options in
195 default 6 if CPU_ARM1136
196 default 6 if CPU_ARM1176
224 This should be enabled if U-Boot needs to communicate with system
242 bool "Build U-Boot using the Thumb instruction set"
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/rk3399_rockchip-uboot/drivers/video/rk_eink/epdlut/
H A Dpvi_waveform.S1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
5 * Author: Zorro Liu <zorro.liu@rock-chips.com>
8 .arch armv8-a+nosimd
18 .file 1 "/home/hzb/sdk/ebc-dev/rk_eink/../epdlut/pvi_waveform.c"
61 mov w0, -1
67 .size get_wf_temp_index, .-get_wf_temp_index
76 stp x29, x30, [sp, -64]!
78 .cfi_offset 29, -64
79 .cfi_offset 30, -56
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H A Drkf_waveform.S1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
5 * Author: Zorro Liu <zorro.liu@rock-chips.com>
8 .arch armv8-a+nosimd
18 .file 1 "/home/hzb/sdk/ebc-dev/rk_eink/../epdlut/rkf_waveform.c"
25 cmp w1, 6
43 .byte (.L3 - .Lrtx4) / 4
44 .byte (.L5 - .Lrtx4) / 4
45 .byte (.L6 - .Lrtx4) / 4
46 .byte (.L7 - .Lrtx4) / 4
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/rk3399_rockchip-uboot/drivers/misc/
H A Drv1126-secure-otp.S1 .arch armv7-a
11 .file "rv1126-secure-otp.c"
24 .file 1 "drivers/misc/rv1126-secure-otp.c"
59 .size rockchip_secure_otp_ioctl, .-rockchip_secure_otp_ioctl
76 .cfi_offset 4, -32
77 .cfi_offset 5, -28
78 .cfi_offset 6, -24
79 .cfi_offset 7, -20
80 .cfi_offset 8, -16
81 .cfi_offset 10, -12
[all …]
H A Drk3588-secure-otp.S1 .arch armv8-a+nosimd
2 .file "rk3588-secure-otp.c"
11 .file 1 "drivers/misc/rk3588-secure-otp.c"
36 mov w0, -22
41 .size secure_otp_ioctl, .-secure_otp_ioctl
50 stp x29, x30, [sp, -48]!
52 .cfi_offset 29, -48
53 .cfi_offset 30, -40
57 .cfi_offset 19, -32
58 .cfi_offset 20, -24
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H A Drk3576-secure-otp.S1 .arch armv8-a+nosimd
2 .file "rk3576-secure-otp.c"
11 .file 1 "drivers/misc/rk3576-secure-otp.c"
36 mov w0, -22
41 .size secure_otp_ioctl, .-secure_otp_ioctl
50 stp x29, x30, [sp, -48]!
52 .cfi_offset 29, -48
53 .cfi_offset 30, -40
57 .cfi_offset 19, -32
58 .cfi_offset 20, -24
[all …]
H A Drv1106-secure-otp.S1 .arch armv7-a
11 .file "rv1106-secure-otp.c"
24 .file 1 "drivers/misc/rv1106-secure-otp.c"
34 @ 58 "drivers/misc/rv1106-secure-otp.c" 1
46 .size rv1106_spl_rockchip_otp_stop, .-rv1106_spl_rockchip_otp_stop
90 .size secure_otp_ioctl, .-secure_otp_ioctl
107 .cfi_offset 4, -24
108 .cfi_offset 5, -20
109 .cfi_offset 6, -16
110 .cfi_offset 7, -12
[all …]
H A Drv1103b-secure-otp.S1 .arch armv7-a
11 .file "rv1103b-secure-otp.c"
24 .file 1 "drivers/misc/rv1103b-secure-otp.c"
34 @ 81 "drivers/misc/rv1103b-secure-otp.c" 1
46 .size rv1103b_spl_rockchip_otp_stop, .-rv1103b_spl_rockchip_otp_stop
90 .size secure_otp_ioctl, .-secure_otp_ioctl
107 .cfi_offset 4, -24
108 .cfi_offset 5, -20
109 .cfi_offset 6, -16
110 .cfi_offset 7, -12
[all …]
H A Drk3506-secure-otp.S1 .arch armv7-a
11 .file "rk3506-secure-otp.c"
24 .file 1 "drivers/misc/rk3506-secure-otp.c"
34 @ 81 "drivers/misc/rk3506-secure-otp.c" 1
46 .size rk3506_spl_rockchip_otp_stop, .-rk3506_spl_rockchip_otp_stop
90 .size secure_otp_ioctl, .-secure_otp_ioctl
107 .cfi_offset 4, -24
108 .cfi_offset 5, -20
109 .cfi_offset 6, -16
110 .cfi_offset 7, -12
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H A Dpx30-secure-otp.S1 .arch armv8-a+nosimd
2 .file "px30-secure-otp.c"
11 .file 1 "drivers/misc/px30-secure-otp.c"
18 // 46 "drivers/misc/px30-secure-otp.c" 1
26 mov w1, -65536
35 // 47 "drivers/misc/px30-secure-otp.c" 1
45 .size px30_spl_rockchip_otp_start, .-px30_spl_rockchip_otp_start
57 // 54 "drivers/misc/px30-secure-otp.c" 1
69 // 55 "drivers/misc/px30-secure-otp.c" 1
77 mov w0, -1
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H A Drk3328-secure-otp.S1 .arch armv8-a+nosimd
2 .file "rk3328-secure-otp.c"
11 .file 1 "drivers/misc/rk3328-secure-otp.c"
18 // 46 "drivers/misc/rk3328-secure-otp.c" 1
30 // 47 "drivers/misc/rk3328-secure-otp.c" 1
42 .size rk3328_spl_rockchip_otp_start, .-rk3328_spl_rockchip_otp_start
54 // 54 "drivers/misc/rk3328-secure-otp.c" 1
66 // 55 "drivers/misc/rk3328-secure-otp.c" 1
77 .size rk3328_spl_rockchip_otp_stop, .-rk3328_spl_rockchip_otp_stop
107 mov w0, -22
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H A Drv1126b-secure-otp.S1 .arch armv8-a+nosimd
2 .file "rv1126b-secure-otp.c"
11 .file 1 "./drivers/misc/rv1126b-secure-otp.c"
18 // 102 "./drivers/misc/rv1126b-secure-otp.c" 1
29 .size rv1126b_spl_rockchip_otp_stop, .-rv1126b_spl_rockchip_otp_stop
38 stp x29, x30, [sp, -32]!
40 .cfi_offset 29, -32
41 .cfi_offset 30, -24
45 .cfi_offset 19, -16
51 // 91 "./drivers/misc/rv1126b-secure-otp.c" 1
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/rk3399_rockchip-uboot/cmd/ddr_tool/ddr_test/
H A Dddr_test_rk1808.S1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 .arch armv8-a+nosimd
21 stp x29, x30, [sp, -144]!
23 .cfi_offset 29, -144
24 .cfi_offset 30, -136
28 .cfi_offset 21, -112
29 .cfi_offset 22, -104
34 .cfi_offset 23, -96
35 .cfi_offset 24, -88
45 .cfi_offset 19, -128
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H A Dddr_test_rk3328.S1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 .arch armv8-a+nosimd
21 stp x29, x30, [sp, -144]!
23 .cfi_offset 29, -144
24 .cfi_offset 30, -136
28 .cfi_offset 21, -112
29 .cfi_offset 22, -104
34 .cfi_offset 23, -96
35 .cfi_offset 24, -88
45 .cfi_offset 19, -128
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H A Dddr_test_px30.S1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 .arch armv8-a+nosimd
21 stp x29, x30, [sp, -144]!
23 .cfi_offset 29, -144
24 .cfi_offset 30, -136
28 .cfi_offset 21, -112
29 .cfi_offset 22, -104
34 .cfi_offset 23, -96
35 .cfi_offset 24, -88
45 .cfi_offset 19, -128
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/rk3399_rockchip-uboot/common/spl/
H A Dspl_fit_tb_rv1106.S1 .arch armv7-a
32 .cfi_offset 4, -24
33 .cfi_offset 5, -20
34 .cfi_offset 6, -16
35 .cfi_offset 7, -12
36 .cfi_offset 8, -8
37 .cfi_offset 14, -4
158 mvn r4, #6
169 .size spl_fit_get_image_name.isra.0, .-spl_fit_get_image_name.isra.0
186 .cfi_offset 4, -12
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H A Dspl_fit_tb_rv1126.S1 .arch armv7-a
32 .cfi_offset 4, -24
33 .cfi_offset 5, -20
34 .cfi_offset 6, -16
35 .cfi_offset 7, -12
36 .cfi_offset 8, -8
37 .cfi_offset 14, -4
158 mvn r4, #6
169 .size spl_fit_get_image_name.isra.0, .-spl_fit_get_image_name.isra.0
186 .cfi_offset 4, -12
[all …]
H A Dspl_fit_tb_arm64.S1 .arch armv8-a+nosimd
15 stp x29, x30, [sp, -80]!
17 .cfi_offset 29, -80
18 .cfi_offset 30, -72
22 .cfi_offset 19, -64
23 .cfi_offset 20, -56
26 .cfi_offset 21, -48
27 .cfi_offset 22, -40
30 .cfi_offset 23, -32
159 mov w19, -22
[all …]
H A Dspl_fit_tb_px30.S1 .arch armv8-a+nosimd
15 stp x29, x30, [sp, -80]!
17 .cfi_offset 29, -80
18 .cfi_offset 30, -72
22 .cfi_offset 19, -64
23 .cfi_offset 20, -56
26 .cfi_offset 21, -48
27 .cfi_offset 22, -40
30 .cfi_offset 23, -32
159 mov w19, -22
[all …]
H A Dspl_fit_tb_rv1126b.S1 .arch armv8-a+nosimd
15 stp x29, x30, [sp, -80]!
17 .cfi_offset 29, -80
18 .cfi_offset 30, -72
22 .cfi_offset 19, -64
23 .cfi_offset 20, -56
26 .cfi_offset 21, -48
27 .cfi_offset 22, -40
30 .cfi_offset 23, -32
159 mov w19, -22
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/rk3399_rockchip-uboot/common/
H A Dspl_mp_boot_rk3528.S1 .arch armv8-a+nosimd
76 stp x29, x30, [sp, -16]!
78 .cfi_offset 29, -16
79 .cfi_offset 30, -8
81 nop // between mem op and mult-accumulate
112 .size mpb_task_set_state, .-mpb_task_set_state
124 .size spl_init_display, .-spl_init_display
136 .size spl_load_baseparamter, .-spl_load_baseparamter
148 .size spl_load_fit, .-spl_load_fit
160 .size spl_load_android, .-spl_load_android
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H A Dmp_boot_rk3528.S1 .arch armv8-a+nosimd
76 stp x29, x30, [sp, -16]!
78 .cfi_offset 29, -16
79 .cfi_offset 30, -8
81 nop // between mem op and mult-accumulate
112 .size mpb_task_set_state, .-mpb_task_set_state
120 stp x29, x30, [sp, -32]!
122 .cfi_offset 29, -32
123 .cfi_offset 30, -24
127 .cfi_offset 19, -16
[all …]
/rk3399_rockchip-uboot/common/smp/
H A Dgeneric_smp64.S1 .arch armv8-a+nosimd
15 stp x29, x30, [sp, -80]!
17 .cfi_offset 29, -80
18 .cfi_offset 30, -72
22 .cfi_offset 23, -32
23 .cfi_offset 24, -24
30 .cfi_offset 19, -64
31 .cfi_offset 20, -56
40 .cfi_offset 21, -48
41 .cfi_offset 22, -40
[all …]

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