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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dexynos5260-clock.txt20 - "fin_pll" - PLL input clock from XXTI
79 - fin_pll
85 - fin_pll
101 - fin_pll
105 - fin_pll
109 - fin_pll
113 - fin_pll
116 - fin_pll
120 - fin_pll
123 - fin_pll
[all …]
H A Dexynos7-clock.txt20 - "fin_pll" - PLL input clock from XXTI
53 - fin_pll
61 - fin_pll
68 - fin_pll
72 - fin_pll
77 - fin_pll
92 - fin_pll
96 - fin_pll
101 - fin_pll
107 - fin_pll
H A Dexynos5410-clock.txt17 defined using standard clock bindings with "fin_pll" clock-output-name.
26 fin_pll: xxti {
29 clock-output-names = "fin_pll";
37 clocks = <&fin_pll>;
H A Dsamsung,s3c64xx-clock.txt31 - "fin_pll" - PLL input clock (xtal/extclk) - required,
49 fin_pll: clock-fin-pll {
51 clock-output-names = "fin_pll";
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos7.c45 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
46 PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
47 PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
48 PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
49 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
174 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
176 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
178 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
180 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
182 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
[all …]
H A Dclk-exynos5260.c88 PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
169 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
171 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
173 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
175 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
177 PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
178 PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
179 PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
180 PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
182 PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
[all …]
H A Dclk-exynos5410.c67 PNAME(apll_p) = { "fin_pll", "fout_apll", };
68 PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
69 PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
70 PNAME(epll_p) = { "fin_pll", "fout_epll" };
71 PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
72 PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
77 PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
78 PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
80 PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", };
82 PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
[all …]
H A Dclk-exynos5420.c297 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
298 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
299 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
300 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
301 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
302 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
303 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
304 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
305 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
306 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
[all …]
H A Dclk-exynos5250.c170 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
173 PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
175 PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
176 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
178 PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
179 PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
180 PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
181 PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
182 PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
188 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
[all …]
H A Dclk-s3c64xx.c86 PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
88 PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
90 PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
93 PNAME(apll_p) = { "fin_pll", "fout_apll" };
94 PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
95 PNAME(epll_p) = { "fin_pll", "fout_epll" };
104 PNAME(clk27_p6410) = { "clk27m", "fin_pll" };
105 PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
106 PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
107 PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
[all …]
H A Dclk-s5pv210.c135 "fin_pll",
140 "fin_pll",
145 "fin_pll",
150 "fin_pll",
251 "fin_pll",
271 "fin_pll",
283 "fin_pll",
304 "fin_pll",
348 "fin_pll",
367 /* PLL input mux (fin_pll), which needs to be registered before PLLs. */
[all …]
H A Dclk-exynos3250.c174 PNAME(mout_vpllsrc_p) = { "fin_pll", };
176 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
177 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
178 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
179 PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
181 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
182 PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
193 = { "fin_pll", "div_aclk_400_mcuisp", };
197 PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };
233 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
[all …]
H A Dclk-exynos4.c279 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
280 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
281 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
282 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
283 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
335 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
353 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
354 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
355 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
1010 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dexynos7420.dtsi16 fin_pll: xxti { label
18 clock-output-names = "fin_pll";
28 clocks = <&fin_pll>;
29 clock-names = "fin_pll";
37 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
41 clock-names = "fin_pll", "dout_sclk_bus0_pll",
51 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
55 clock-names = "fin_pll", "dout_aclk_peric1_66",
H A Dexynos7420-espresso7420.dts22 &fin_pll {
H A Dexynos4x12.dtsi49 clock-names = "fin_pll", "mct";
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi41 fin_pll: clock { label
44 clock-output-names = "fin_pll";
142 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
146 clock-names = "fin_pll", "dout_sclk_bus0_pll",
155 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
159 clock-names = "fin_pll", "dout_sclk_bus0_pll",
168 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
169 clock-names = "fin_pll", "dout_aclk_ccore_133";
176 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
178 clock-names = "fin_pll", "dout_aclk_peric0_66",
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml32 - pattern: "^(fin_pll|mct)$"
33 - pattern: "^(fin_pll|mct)$"
80 clock-names = "fin_pll", "mct";
100 clock-names = "fin_pll", "mct";
121 clock-names = "fin_pll", "mct";
141 clock-names = "fin_pll", "mct";
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Ds3c6410-smdk6410.dts31 fin_pll: oscillator-0 { label
34 clock-output-names = "fin_pll";
65 clocks = <&fin_pll>;
H A Ds3c6410-mini6410.dts31 fin_pll: oscillator-0 { label
34 clock-output-names = "fin_pll";
161 clocks = <&fin_pll>;
H A Dexynos5260-xyref5260.dts25 fin_pll: xxti { label
28 clock-output-names = "fin_pll";
H A Dexynos5410.dtsi72 clocks = <&fin_pll>;
86 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
323 clocks = <&fin_pll>, <&clock CLK_MCT>;
324 clock-names = "fin_pll", "mct";
H A Dexynos5410-smdk5410.dts25 fin_pll: xxti { label
28 clock-output-names = "fin_pll";
H A Dexynos5410-odroidxu.dts45 fin_pll: xxti { label
48 clock-output-names = "fin_pll";
98 clocks = <&fin_pll>;
H A Dexynos5260.dtsi184 clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
185 clock-names = "fin_pll", "mct";

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