| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/dsa/ |
| H A D | ocelot.txt | 5 -----
9 - VSC9959 (Felix)
10 - VSC9953 (Seville)
13 larger ENETC root complex. As a result, the ethernet-switch node is a sub-node
18 in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0).
25 For the external switch ports, depending on board configuration, "phy-mode" and
26 "phy-handle" are populated by board specific device tree instances. Ports 4 and
27 5 are fixed as internal ports in the NXP LS1028A instantiation.
29 The CPU port property ("ethernet") configures the feature called "NPI port" in
31 connected, in the Node Processor Interface (NPI) mode, to an Ethernet port.
[all …]
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| H A D | dsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Switch Device Tree Bindings
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vivien Didelot <vivien.didelot@gmail.com>
15 This binding represents Ethernet Switches which have a dedicated CPU
16 port. That port is usually connected to an Ethernet Controller of the
33 $ref: /schemas/types.yaml#/definitions/uint32-array
[all …]
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| H A D | mt7530.txt | 1 Mediatek MT7530 Ethernet switch
6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3288/ |
| H A D | Kconfig | 4 bool "Google/Rockchip Veyron-Jerry Chromebook"
7 Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
8 HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
9 WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
13 bool "Google/Rockchip Veyron-Mickey Chromebit"
16 Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
23 bool "Google/Rockchip Veyron-Minnie Chromebook"
26 Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
27 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
29 EC (Cortex-M3) to provide access to the keyboard and battery
[all …]
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| /OK3568_Linux_fs/u-boot/arch/mips/mach-bmips/ |
| H A D | Kconfig | 88 bool "Comtrend AR-5387un"
92 Comtrend AR-5387un boards have a BCM6328 SoC with 64 MB of RAM and 16
95 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
99 bool "Comtrend CT-5361"
103 Comtrend CT-5361 boards have a BCM6348 SoC with 16 MB of RAM and 4 MB
106 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a
110 bool "Comtrend VR-3032u board"
114 Comtrend VR-3032u boards have a BCM63268 SoC with 64 MB of RAM and
117 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
128 ethernet ports, 3 USB ports, 1 UART, GPIO buttons and LEDs, and
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/networking/dsa/ |
| H A D | configuration.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 .. _dsa-config-showcases:
13 -----------------------
19 Every switch port acts as a different configurable Ethernet port
22 Every switch port is part of one configurable Ethernet bridge
26 Ethernet bridge.
27 The upstream port acts as different configurable Ethernet port.
32 Through DSA every port of a switch is handled like a normal linux Ethernet
33 interface. The CPU port is the switch port connected to an Ethernet MAC chip.
34 The corresponding linux Ethernet interface is called the master interface.
[all …]
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| H A D | dsa.rst | 14 to support Marvell Ethernet switches (MV88E6xxx, a.k.a Linkstreet product line)
22 An Ethernet switch is typically comprised of multiple front-panel ports, and one
24 presence of a management port connected to an Ethernet controller capable of
25 receiving Ethernet frames from the switch. This is a very common setup for all
26 kinds of Ethernet switches found in Small Home and Office products: routers,
27 gateways, or even top-of-the rack switches. This host Ethernet controller will
32 using upstream and downstream Ethernet links between switches. These specific
33 ports are referred to as "dsa" ports in DSA terminology and code. A collection
36 For each front-panel port, DSA will create specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
[all …]
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| H A D | lan9303.rst | 2 LAN9303 Ethernet switch driver
5 The LAN9303 is a three port 10/100 Mbps ethernet switch with integrated phys for
6 the two external ethernet ports. The third port is an RMII/MII interface to a
24 When both user ports are joined to the same bridge, the normal HW MAC learning
29 If one of the user ports leave the bridge, the ports goes back to the initial
36 - Support for VLAN filtering is not implemented
37 - The HW does not support VLAN-specific fdb entries
|
| /OK3568_Linux_fs/u-boot/drivers/net/phy/ |
| H A D | Kconfig | 3 bool "Bit-banged ethernet MII management channel support"
9 bool "Ethernet PHY (physical media interface) support"
11 Enable Ethernet PHY (physical media interface) support.
16 bool "Marvel MV88E61xx Ethernet switch PHY support."
24 hex "Bitmask of PHY Ports"
27 hex "Bitmask of PHYless serdes Ports"
35 bool "Aquantia Ethernet PHYs support"
38 bool "Atheros Ethernet PHYs support"
41 bool "Broadcom Ethernet PHYs support"
44 bool "Cortina Ethernet PHYs support"
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/ |
| H A D | ti,cpsw-switch.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
15 communication and can be configured as an ethernet switch. It provides the
24 - const: ti,cpsw-switch
[all …]
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| H A D | fsl-fman.txt | 5 - FMan Node
6 - FMan Port Node
7 - FMan MURAM Node
8 - FMan dTSEC/XGEC/mEMAC Node
9 - FMan IEEE 1588 Node
10 - FMan MDIO Node
11 - Example
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
23 - compatible
32 - cell-index
[all …]
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| H A D | hisilicon-hns-nic.txt | 4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
12 are called debug ports.
16 In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
17 port-id can be 2 to 7. Here is the diagram:
18 +-----+---------------+
[all …]
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| H A D | mscc-ocelot.txt | 8 - compatible: Should be "mscc,vsc7514-switch"
9 - reg: Must contain an (offset, length) pair of the register set for each
10 entry in reg-names.
11 - reg-names: Must include the following entries:
12 - "sys"
13 - "rew"
14 - "qs"
15 - "ptp" (optional due to backward compatibility)
16 - "qsys"
17 - "ana"
[all …]
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| H A D | ti,k3-am654-cpsw-nuss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15 (one external) and provides Ethernet packet communication for the device.
16 CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
[all …]
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| H A D | cavium-pip.txt | 1 * PIP Ethernet nexus.
3 The PIP Ethernet nexus can control several data packet input/output
5 several interfaces, and each interface may have several ports. These
6 ports might be an individual Ethernet PHY.
10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/t1040qds/ |
| H A D | README | 2 --------
7 ------------------
8 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
16 - Interconnect CoreNet platform
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
21 - Packet parsing, classification, and distribution
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/t104xrdb/ |
| H A D | README | 2 --------
9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
16 The board is re-designed T1040RDB board with following changes :
17 - Support of DDR4 memory and some enhancements
20 The board is re-designed T1040RDB board with following changes :
21 - Support of DDR4 memory
22 - Support for 0x86 serdes protocol which can support following interfaces
23 - 2 RGMII's on DTSEC4, DTSEC5
24 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
27 -------------------------------------------------------------------------
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/dsa/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 tristate "Broadcom Starfighter 2 Ethernet switch support"
16 This enables support for the Broadcom Starfighter 2 Ethernet
20 tristate "DSA mock-up Ethernet switch chip support"
24 This enables support for a fake mock-up switch chip which
36 tristate "MediaTek MT753x and MT7621 Ethernet switch support"
42 Ethernet switch chips.
45 tristate "Marvell 88E6060 ethernet switch chip support"
49 This enables support for the Marvell 88E6060 ethernet switch
63 tristate "Qualcomm Atheros QCA8K Ethernet switch family support"
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/t208xrdb/ |
| H A D | README | 1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
[all …]
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| /OK3568_Linux_fs/kernel/net/dsa/ |
| H A D | dsa2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * net/dsa/dsa2.c - Hardware switch handling, binding version 2
4 * Copyright (c) 2008-2009 Marvell Semiconductor
30 if (dst->index != tree_index) in dsa_switch_find()
33 list_for_each_entry(dp, &dst->ports, list) { in dsa_switch_find()
34 if (dp->ds->index != sw_index) in dsa_switch_find()
37 return dp->ds; in dsa_switch_find()
50 if (dst->index == index) in dsa_tree_find()
64 dst->index = index; in dsa_tree_alloc()
66 INIT_LIST_HEAD(&dst->rtable); in dsa_tree_alloc()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/staging/fsl-dpaa2/ethsw/ |
| H A D | README | 1 DPAA2 Ethernet Switch driver
4 This file provides documentation for the DPAA2 Ethernet Switch driver
11 Creating an Ethernet Switch
23 The Ethernet Switch in the DPAA2 architecture consists of several hardware
31 drivers/staging/fsl-mc/README.txt
33 The Ethernet Switch is built on top of a Datapath Switch (DPSW) object.
37 ---------------------
39 ---------------------
42 ----------
44 ----------
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/t208xqds/ |
| H A D | README | 1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/team/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Ethernet team driver support"
6 multiple ethernet devices.
22 Basic mode where packets are transmitted always by all suitable ports.
24 All added ports are setup to have team's device address.
30 tristate "Round-robin mode support"
34 round-robin fashion using packet counter.
36 All added ports are setup to have team's device address.
48 All added ports are setup to have team's device address.
54 tristate "Active-backup mode support"
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/t102xrdb/ |
| H A D | README | 2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
[all …]
|