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Searched +full:emc +full:- +full:timings +full:- +full:0 (Results 1 – 25 of 28) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
24 #define EMC_INTSTATUS 0x000
25 #define EMC_INTMASK 0x004
26 #define EMC_DBG 0x008
27 #define EMC_TIMING_CONTROL 0x028
28 #define EMC_RC 0x02c
29 #define EMC_RFC 0x030
30 #define EMC_RAS 0x034
31 #define EMC_RP 0x038
32 #define EMC_R2W 0x03c
[all …]
H A Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
31 #define EMC_INTSTATUS 0x000
32 #define EMC_INTMASK 0x004
33 #define EMC_DBG 0x008
34 #define EMC_CFG 0x00c
35 #define EMC_REFCTRL 0x020
36 #define EMC_TIMING_CONTROL 0x028
[all …]
H A Dtegra210-emc-table.c1 // SPDX-License-Identifier: GPL-2.0
8 #include "tegra210-emc.h"
15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local
16 struct tegra210_emc_timing *timings; in tegra210_emc_table_device_init() local
17 unsigned int i, count = 0; in tegra210_emc_table_device_init()
19 timings = memremap(rmem->base, rmem->size, MEMREMAP_WB); in tegra210_emc_table_device_init()
20 if (!timings) { in tegra210_emc_table_device_init()
21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init()
22 return -ENOMEM; in tegra210_emc_table_device_init()
25 count = 0; in tegra210_emc_table_device_init()
[all …]
H A Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
27 (0x7 << EMC_CLK_EMC_2X_CLK_SRC_SHIFT)
28 #define EMC_CLK_SOURCE_PLLM_LJ 0x4
29 #define EMC_CLK_SOURCE_PLLMB_LJ 0x5
32 #define EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT 0
34 (0xff << EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT)
39 (0x7 << DLL_CLK_EMC_DLL_CLK_SRC_SHIFT)
[all …]
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
21 #include <soc/tegra/emc.h>
25 #define EMC_FBIO_CFG5 0x104
26 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
27 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
29 #define EMC_INTSTATUS 0x0
32 #define EMC_CFG 0xc
37 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
40 #define EMC_REFCTRL 0x20
[all …]
H A Dtegra210-emc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #define EMC_INTSTATUS 0x0
23 #define EMC_DBG 0x8
26 #define EMC_CFG 0xc
31 #define EMC_PIN 0x24
32 #define EMC_PIN_PIN_CKE BIT(0)
35 #define EMC_TIMING_CONTROL 0x28
36 #define EMC_RC 0x2c
37 #define EMC_RFC 0x30
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
[all …]
H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]
H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
[all …]
H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
39 const: nvidia,tegra30-mc
47 clock-names:
49 - const: mc
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
24 #include <soc/tegra/emc.h>
28 #define CLK_SOURCE_EMC 0x19c
30 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
36 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
46 * List of clock sources for various parents the EMC clock can have.
52 #define EMC_SRC_PLL_M 0
[all …]
H A Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #define CLK_SOURCE_EMC 0x19c
20 #define CLK_SOURCE_EMC_2X_CLK_DIVISOR GENMASK(7, 0)
22 #define CLK_SRC_PLLM 0
53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-car.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
20 - #reset-cells : Should be 1.
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
7 * Tilapia's memory timings are pretty much the same as the Grouper's
9 * these differentiating timings are overridden here for Tilapia.
12 memory-controller@7000f400 {
13 emc-timings-0 {
14 timing-667000000 {
15 clock-frequency = <667000000>;
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
H A Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
9 emc-timings-1 {
10 nvidia,ram-code = <1>;
12 timing-12750000 {
13 clock-frequency = <12750000>;
14 nvidia,parent-clock-frequency = <408000000>;
16 clock-names = "emc-parent";
18 timing-20400000 {
19 clock-frequency = <20400000>;
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
8 timing-25500000 {
9 clock-frequency = <25500000>;
11 nvidia,emem-configuration = <
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
[all …]
H A Dtegra124-nyan-big-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 nvidia,long-ram-code;
8 emc-timings-1 {
9 nvidia,ram-code = <1>;
11 timing-12750000 {
12 clock-frequency = <12750000>;
13 nvidia,parent-clock-frequency = <408000000>;
15 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c5 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
14 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/arch/emc.h>
26 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; variable
32 /* Enable EMC interface and choose little endian mode */ in ddr_init()
33 writel(1, &emc->ctrl); in ddr_init()
34 writel(0, &emc->config); in ddr_init()
35 /* Select maximum EMC Dynamic Memory Refresh Time */ in ddr_init()
36 writel(0x7FF, &emc->refresh); in ddr_init()
40 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init()
[all …]
/OK3568_Linux_fs/u-boot/board/timll/devkit3250/
H A Ddevkit3250.c4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/emc.h>
19 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; variable
26 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); in reset_periph()
27 writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); in reset_periph()
30 writel(0, &wdt->mctrl); in reset_periph()
31 clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); in reset_periph()
51 return 0; in board_early_init_f()
57 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/
H A Demc.c4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch-tegra/ap.h>
11 #include <asm/arch-tegra/apb_misc.h>
13 #include <asm/arch/emc.h>
17 * The EMC registers have shadow registers. When the EMC clock is updated
21 * and relies on the clock lock on the emc clock to avoid races between
31 0x2c, /* RC */
32 0x30, /* RFC */
33 0x34, /* RAS */
34 0x38, /* RP */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dtegra20-seaboard.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
31 stdout-path = &uartd;
35 reg = <0x00000000 0x40000000>;
47 display-timings {
48 timing@0 {
50 clock-frequency = <70600000>;
53 hback-porch = <58>;
54 hfront-porch = <58>;
55 hsync-len = <58>;
[all …]
/OK3568_Linux_fs/u-boot/lib/
H A Dfdtdec.c3 * SPDX-License-Identifier: GPL-2.0+
29 * good reason why driver-model conversion is infeasible. Examples include
35 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
36 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
37 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
38 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
39 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
41 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
42 COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
43 COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"),
[all …]
/OK3568_Linux_fs/buildroot/output/OK3568/target/usr/lib/modules/5.10.160/
H A Dmodules.builtin.modinfo

12