Searched +full:emc +full:- +full:mrs +full:- +full:wait +full:- +full:cnt (Results 1 – 8 of 8) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.04 emc-timings-1 {5 nvidia,ram-code = <1>;7 timing-12750000 {8 clock-frequency = <12750000>;9 nvidia,parent-clock-frequency = <408000000>;11 clock-names = "emc-parent";13 timing-20400000 {14 clock-frequency = <20400000>;15 nvidia,parent-clock-frequency = <408000000>;[all …]
1 // SPDX-License-Identifier: GPL-2.0 OR X113 * Copyright 2016-2019 Toradex AG9 emc-timings-1 {10 nvidia,ram-code = <1>;12 timing-12750000 {13 clock-frequency = <12750000>;14 nvidia,parent-clock-frequency = <408000000>;16 clock-names = "emc-parent";18 timing-20400000 {19 clock-frequency = <20400000>;[all …]
1 // SPDX-License-Identifier: GPL-2.04 emc-timings-3 {5 nvidia,ram-code = <3>;7 timing-12750000 {8 clock-frequency = <12750000>;9 nvidia,parent-clock-frequency = <408000000>;11 clock-names = "emc-parent";13 timing-20400000 {14 clock-frequency = <20400000>;15 nvidia,parent-clock-frequency = <408000000>;[all …]
1 // SPDX-License-Identifier: GPL-2.04 nvidia,long-ram-code;8 emc-timings-1 {9 nvidia,ram-code = <1>;11 timing-12750000 {12 clock-frequency = <12750000>;13 nvidia,parent-clock-frequency = <408000000>;15 clock-names = "emc-parent";17 timing-20400000 {18 clock-frequency = <20400000>;[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>14 The EMC interfaces with the off-chip SDRAM to service the request stream19 const: nvidia,tegra124-emc26 - description: external memory clock28 clock-names:[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 #include <linux/clk-provider.h>21 #include <soc/tegra/emc.h>277 /* Maximum amount of time in us. to wait for changes to become effective */488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()495 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * Based on downstream driver from NVIDIA and tegra124-emc.c6 * Copyright (C) 2011-2014 NVIDIA Corporation9 * Copyright (C) 2019 GRATE-DRIVER project357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()377 struct tegra_emc *emc = data; in tegra_emc_isr() local381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()[all …]
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