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/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/adv7511/
H A Dadv7533.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct mipi_dsi_device *dsi = adv->dsi; in adv7511_dsi_config_timing_gen() local
30 struct drm_display_mode *mode = &adv->curr_mode; in adv7511_dsi_config_timing_gen()
32 u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */ in adv7511_dsi_config_timing_gen()
34 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
35 hfp = mode->hsync_start - mode->hdisplay; in adv7511_dsi_config_timing_gen()
36 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
37 vsw = mode->vsync_end - mode->vsync_start; in adv7511_dsi_config_timing_gen()
38 vfp = mode->vsync_start - mode->vdisplay; in adv7511_dsi_config_timing_gen()
39 vbp = mode->vtotal - mode->vsync_end; in adv7511_dsi_config_timing_gen()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
83 * The DSI host controller needs this reset sequence according to NWL:
84 * 1. Deassert pclk reset to get access to DSI regs
85 * 2. Configure DSI Host and DPHY and enable DPHY
87 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
89 * DSI data
91 * TODO: Since panel_bridges do their DSI setup in enable we
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H A Dcdns-dsi.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <linux/phy/phy-mipi-dphy.h>
71 #define DATA_LANE_EN(x) BIT((x) - 1)
488 return mode->hsync_start - mode->hdisplay; in mode_to_dpi_hfp()
490 return mode->crtc_hsync_start - mode->crtc_hdisplay; in mode_to_dpi_hfp()
502 dsi_timing -= dsi_pkt_overhead; in dpi_to_dsi_timing()
507 static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, in cdns_dsi_mode2cfg() argument
512 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
519 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in cdns_dsi_mode2cfg()
522 bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format); in cdns_dsi_mode2cfg()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/synopsys/
H A Ddw-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
199 #define N_LANES(n) (((n) - 1) & 0x3)
232 #define VPG_DEFS(name, dsi) \ argument
233 ((void __force *)&((*dsi).vpg_defs.name))
235 #define REGISTER(name, mask, dsi) \ argument
236 { #name, VPG_DEFS(name, dsi), mask, dsi }
242 struct dw_mipi_dsi *dsi; member
260 u32 lanes; member
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/tegra/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
40 unsigned int lanes; member
71 unsigned int lanes; member
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/kirin/kirin/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 Hisilicon Limited.
65 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
66 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
68 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
69 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
70 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
104 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
105 phy->pll_pre_div1p = 1; in dsi_calc_phy_rate()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk628/
H A Drk628_dsi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
223 u32 lanes; member
243 static inline void dsi_write(struct rk628_dsi *dsi, u32 reg, u32 val) in dsi_write() argument
245 regmap_write(dsi->regmap, dsi->reg_base + reg, val); in dsi_write()
248 static inline u32 dsi_read(struct rk628_dsi *dsi, u32 reg) in dsi_read() argument
252 regmap_read(dsi->regmap, dsi->reg_base + reg, &val); in dsi_read()
257 static inline void dsi_update_bits(struct rk628_dsi *dsi, u32 reg, u32 mask, in dsi_update_bits() argument
262 orig = dsi_read(dsi, reg); in dsi_update_bits()
265 dsi_write(dsi, reg, tmp); in dsi_update_bits()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/vc4/
H A Dvc4_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
146 * of going to LP-STOP.
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/msm/
H A Ddsi.txt1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
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/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Ddw_mipi_dsi.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch-rockchip/clock.h>
163 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
225 /* Non-SNPS PHY */
244 u32 lanes; member
254 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) in dsi_write() argument
256 writel(val, dsi->base + reg); in dsi_write()
259 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) in dsi_read() argument
261 return readl(dsi->base + reg); in dsi_read()
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H A Drk618_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
10 #include <dm/device-internal.h>
223 unsigned int lanes; member
244 #define dsi_read_poll_timeout(dsi, addr, val, cond, sleep_us, timeout_us) \ argument
248 (val) = dsi_read(dsi, addr); \
252 (val) = dsi_read(dsi, addr); \
258 (cond) ? 0 : -ETIMEDOUT; \
261 static inline int dsi_write(struct rk618_dsi *dsi, u32 reg, u32 val) in dsi_write() argument
263 return rk618_i2c_write(dsi->parent, reg, val); in dsi_write()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/ti/
H A Dti,omap5-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
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H A Dti,omap4-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/kirin/kirin960/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 Hisilicon Limited.
39 #define DTS_COMP_DSI_NAME "hisilicon,hi3660-dsi"
40 #define DSS_REDUCE(x) ((x) > 0 ? ((x) - 1) : (x))
61 u32 mask = (1UL << bw) - 1UL; in set_reg()
80 DRM_DEBUG_DRIVER("Checking mode %ix%i@%i clock: %i...", mode->hdisplay, in dsi_encoder_phy_mode_valid()
81 mode->vdisplay, drm_mode_vrefresh(mode), mode->clock); in dsi_encoder_phy_mode_valid()
82 if ((mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 148500) || in dsi_encoder_phy_mode_valid()
83 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 80192) || in dsi_encoder_phy_mode_valid()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/panel/
H A Draydium,rm67191.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raydium RM67171 OLED LCD panel with MIPI-DSI protocol
10 - Robert Chiras <robert.chiras@nxp.com>
13 - $ref: panel-common.yaml#
21 reset-gpios: true
22 width-mm: true
23 height-mm: true
25 dsi-lanes:
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk618/
H A Drk618_dsi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
233 unsigned int lanes; member
282 static void rk618_dsi_set_hs_clk(struct rk618_dsi *dsi) in rk618_dsi_set_hs_clk() argument
284 const struct drm_display_mode *mode = &dsi->mode; in rk618_dsi_set_hs_clk()
285 struct mipi_dphy *phy = &dsi->phy; in rk618_dsi_set_hs_clk()
286 struct device *dev = dsi->dev; in rk618_dsi_set_hs_clk()
291 if (!of_property_read_u32(dev->of_node, "rockchip,lane-rate", &value)) { in rk618_dsi_set_hs_clk()
294 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in rk618_dsi_set_hs_clk()
295 unsigned int lanes = dsi->lanes; in rk618_dsi_set_hs_clk() local
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/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_dsi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Guochun Huang <hero.huang@rock-chips.com>
46 /* MIPI DSI Processor-to-Peripheral transaction types */
97 /* MIPI DSI Peripheral-to-Processor transaction types */
164 * struct mipi_dsi_msg - read/write DSI buffer
186 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
200 static inline int dsi_write(struct rk628 *rk628, const struct rk628_dsi *dsi, in dsi_write() argument
205 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in dsi_write()
210 static inline int dsi_read(struct rk628 *rk628, const struct rk628_dsi *dsi, in dsi_read() argument
215 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in dsi_read()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/panel/
H A Dpanel-sitronix-st7703.c1 // SPDX-License-Identifier: GPL-2.0
5 * - Rocktech jh057n00900 5.5" MIPI-DSI panel
13 #include <linux/media-bus-format.h>
26 #define DRV_NAME "panel-sitronix-st7703"
28 /* Manufacturer specific Commands send via DSI */
65 unsigned int lanes; member
76 #define dsi_generic_write_seq(dsi, seq...) do { \ argument
79 ret = mipi_dsi_generic_write(dsi, d, ARRAY_SIZE(d)); \
86 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in jh057n_init_sequence() local
93 dsi_generic_write_seq(dsi, ST7703_CMD_SETEXTC, in jh057n_init_sequence()
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H A Dpanel-boe-tv101wum-nl6.c1 // SPDX-License-Identifier: GPL-2.0
37 unsigned int lanes; member
43 struct mipi_dsi_device *dsi; member
436 struct mipi_dsi_device *dsi = boe->dsi; in boe_panel_init_dcs_cmd() local
437 struct drm_panel *panel = &boe->base; in boe_panel_init_dcs_cmd()
440 if (boe->desc->init_cmds) { in boe_panel_init_dcs_cmd()
441 const struct panel_init_cmd *init_cmds = boe->desc->init_cmds; in boe_panel_init_dcs_cmd()
446 switch (cmd->type) { in boe_panel_init_dcs_cmd()
448 msleep(cmd->data[0]); in boe_panel_init_dcs_cmd()
453 err = mipi_dsi_dcs_write(dsi, cmd->data[0], in boe_panel_init_dcs_cmd()
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/OK3568_Linux_fs/u-boot/include/drm/
H A Ddrm_mipi_dsi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * MIPI DSI Bus
5 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
25 * struct mipi_dsi_msg - read/write DSI buffer
50 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
68 * struct mipi_dsi_host_ops - DSI bus operations
69 * @attach: attach DSI device to DSI host
70 * @detach: detach DSI device from DSI host
71 * @transfer: transmit a DSI packet
73 * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/mcde/
H A Dmcde_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
32 /* PRCMU DSI reset registers */
73 d = host_to_mcde_dsi(mdsi->host); in mcde_dsi_irq()
75 dev_dbg(d->dev, "%s called\n", __func__); in mcde_dsi_irq()
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
81 dev_dbg(d->dev, "direct command write completed\n"); in mcde_dsi_irq()
84 dev_dbg(d->dev, "direct command TE received\n"); in mcde_dsi_irq()
87 dev_err(d->dev, "direct command ACK ERR received\n"); in mcde_dsi_irq()
89 dev_err(d->dev, "direct command read ERR received\n"); in mcde_dsi_irq()
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/OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/
H A Drk628_dsi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Shunqing Chen <csq@rock-chips.com>
61 static void mipi_dphy_power_on_dsi(struct rk628_dsi *dsi) in mipi_dphy_power_on_dsi() argument
67 struct rk628 *rk628 = dsi->rk628; in mipi_dphy_power_on_dsi()
75 testif_testclr_assert(dsi->rk628); in mipi_dphy_power_on_dsi()
83 testif_testclr_deassert(dsi->rk628); in mipi_dphy_power_on_dsi()
85 mipi_dphy_init_hsfreqrange(dsi->rk628, dsi->lane_mbps); in mipi_dphy_power_on_dsi()
96 ret = regmap_read_poll_timeout(rk628->regmap[dev_id], in mipi_dphy_power_on_dsi()
100 dev_err(rk628->dev, "PHY is not locked\n"); in mipi_dphy_power_on_dsi()
105 ret = regmap_read_poll_timeout(rk628->regmap[dev_id], in mipi_dphy_power_on_dsi()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/omapdrm/dss/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #define DSS_SUBSYS_NAME "DSI"
47 /* DSI Protocol Engine */
111 #define REG_GET(dsi, idx, start, end) \ argument
112 FLD_GET(dsi_read_reg(dsi, idx), start, end)
114 #define REG_FLD_MOD(dsi, idx, val, start, end) \ argument
115 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
207 static int dsi_display_init_dispc(struct dsi_data *dsi);
208 static void dsi_display_uninit_dispc(struct dsi_data *dsi);
210 static int dsi_vc_send_null(struct dsi_data *dsi, int channel);
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/OK3568_Linux_fs/kernel/include/drm/
H A Ddrm_mipi_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * MIPI DSI Bus
5 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
28 * struct mipi_dsi_msg - read/write DSI buffer
57 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
75 * struct mipi_dsi_host_ops - DSI bus operations
76 * @attach: attach DSI device to DSI host
77 * @detach: detach DSI device from DSI host
78 * @transfer: transmit a DSI packet
80 * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
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