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/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-csi2-dphy.c3 * Rockchip MIPI CSI2 DPHY driver
25 #include "phy-rockchip-csi2-dphy-common.h"
56 struct csi2_dphy *dphy = to_csi2_dphy(sd); in get_remote_sensor() local
58 if (dphy->num_sensors == 0) in get_remote_sensor()
63 v4l2_warn(sd, "No link between dphy and sensor\n"); in get_remote_sensor()
71 static struct csi2_sensor *sd_to_sensor(struct csi2_dphy *dphy, in sd_to_sensor() argument
76 for (i = 0; i < dphy->num_sensors; ++i) in sd_to_sensor()
77 if (dphy->sensors[i].sd == sd) in sd_to_sensor()
78 return &dphy->sensors[i]; in sd_to_sensor()
85 struct csi2_dphy *dphy = to_csi2_dphy(sd); in csi2_dphy_get_sensor_data_rate() local
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H A Dphy-rockchip-csi2-dphy-hw.c3 * Rockchip MIPI CSI2 DPHY driver
25 #include "phy-rockchip-csi2-dphy-common.h"
27 /* RK3562 DPHY GRF REG OFFSET */
35 /*RK3588 DPHY GRF REG OFFSET */
39 /*RV1106 DPHY GRF REG OFFSET */
494 v4l2_warn(sd, "No link between dphy and sensor\n"); in get_remote_sensor()
502 static struct csi2_sensor *sd_to_sensor(struct csi2_dphy *dphy, in sd_to_sensor() argument
507 for (i = 0; i < dphy->num_sensors; ++i) in sd_to_sensor()
508 if (dphy->sensors[i].sd == sd) in sd_to_sensor()
509 return &dphy->sensors[i]; in sd_to_sensor()
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H A Dphy-rockchip-csi2-dphy-common.h3 * Rockchip MIPI CSI2 DPHY driver
104 int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
105 int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
129 int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
130 int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
H A Dphy-rockchip-dphy-rx0.c3 * Rockchip MIPI Synopsys DPHY RX0 driver
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
201 /* dphy start */ in rk_dphy_enable()
317 .compatible = "rockchip,rk3399-mipi-dphy-rx0",
381 .name = "rockchip-mipi-dphy-rx0",
388 MODULE_DESCRIPTION("Rockchip MIPI Synopsys DPHY RX0 driver");
H A Dphy-rockchip-samsung-dcphy.c23 #include "phy-rockchip-csi2-dphy-common.h"
1291 * dphy: 400mv in samsung_mipi_dcphy_bias_block_enable()
1871 * All DPHY 2.0 compliant Transmitters shall support SSC operating above in samsung_mipi_dcphy_pll_calc_rate()
1910 v4l2_warn(sd, "No link between dphy and sensor\n"); in get_remote_sensor()
1918 static struct csi2_sensor *sd_to_sensor(struct csi2_dphy *dphy, in sd_to_sensor() argument
1923 for (i = 0; i < dphy->num_sensors; ++i) in sd_to_sensor()
1924 if (dphy->sensors[i].sd == sd) in sd_to_sensor()
1925 return &dphy->sensors[i]; in sd_to_sensor()
1930 static void samsung_dcphy_rx_config_settle(struct csi2_dphy *dphy, in samsung_dcphy_rx_config_settle() argument
1933 struct samsung_mipi_dcphy *samsung = dphy->samsung_phy; in samsung_dcphy_rx_config_settle()
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H A DKconfig13 Enable this to support the Rockchip CSI2 DPHY.
23 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
28 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
32 will be called phy-rockchip-dphy-rx0.
H A DMakefile2 obj-$(CONFIG_PHY_ROCKCHIP_CSI2_DPHY) += phy-rockchip-csi2-dphy-hw.o \
3 phy-rockchip-csi2-dphy.o
5 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
/OK3568_Linux_fs/kernel/drivers/phy/cadence/
H A Dcdns-dphy.c16 #include <linux/phy/phy-mipi-dphy.h>
21 /* DPHY registers */
76 int (*probe)(struct cdns_dphy *dphy);
77 void (*remove)(struct cdns_dphy *dphy);
78 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
79 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
81 void (*set_pll_cfg)(struct cdns_dphy *dphy,
83 unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
95 static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, in cdns_dsi_get_dphy_pll_cfg() argument
100 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); in cdns_dsi_get_dphy_pll_cfg()
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/OK3568_Linux_fs/kernel/drivers/phy/allwinner/
H A Dphy-sun6i-mipi-dphy.c18 #include <linux/phy/phy-mipi-dphy.h>
99 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init() local
101 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
102 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
103 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
110 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_configure() local
117 memcpy(&dphy->config, opts, sizeof(dphy->config)); in sun6i_dphy_configure()
124 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_power_on() local
125 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); in sun6i_dphy_power_on()
127 regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, in sun6i_dphy_power_on()
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/OK3568_Linux_fs/kernel/drivers/media/spi/
H A Drk1608_dphy.c32 #define RK1608_DPHY_NAME "RK1608-dphy"
696 static int rk1608_initialize_controls(struct rk1608_dphy *dphy) in rk1608_initialize_controls() argument
701 u32 idx = dphy->fmt_inf_idx; in rk1608_initialize_controls()
706 handler = &dphy->ctrl_handler; in rk1608_initialize_controls()
711 dphy->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, in rk1608_initialize_controls()
713 0, &dphy->link_freqs); in rk1608_initialize_controls()
714 if (dphy->link_freq) in rk1608_initialize_controls()
715 dphy->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; in rk1608_initialize_controls()
717 switch (dphy->fmt_inf[idx].data_type) { in rk1608_initialize_controls()
728 pixel_rate = dphy->link_freqs * dphy->fmt_inf[idx].mipi_lane * 2; in rk1608_initialize_controls()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Drockchip-mipi-dphy.txt6 "rockchip,rk1808-mipi-dphy-rx"
7 "rockchip,rk3288-mipi-dphy"
8 "rockchip,rk3326-mipi-dphy"
9 "rockchip,rk3368-mipi-dphy"
10 "rockchip,rk3399-mipi-dphy"
11 "rockchip,rv1126-csi-dphy"
31 The first port show the sensors connected in this mipi-dphy.
61 mipi_dphy_rx0: mipi-dphy-rx0 {
62 compatible = "rockchip,rk3399-mipi-dphy";
66 clock-names = "dphy-ref", "dphy-cfg", "grf";
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dcdns,dphy.txt1 Cadence DPHY
4 Cadence DPHY block.
7 - compatible: should be set to "cdns,dphy".
8 - reg: physical base address and length of the DPHY registers.
9 - clocks: DPHY reference clocks.
14 dphy0: dphy@fd0e0000{
15 compatible = "cdns,dphy";
H A Drockchip-mipi-dphy-rx0.yaml4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
19 const: rockchip,rk3399-mipi-dphy-rx0
29 - const: dphy-ref
30 - const: dphy-cfg
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
70 clock-names = "dphy-ref", "dphy-cfg", "grf";
H A Dphy-rockchip-inno-mipi-dphy.txt1 ROCKCHIP MIPI DPHY WITH INNO IP BLOCK
5 "rockchip,rk1808-mipi-dphy";
6 "rockchip,rv1126-mipi-dphy";
7 - reg : the address offset of register for mipi-dphy configuration.
21 mipi_dphy: mipi-dphy@ff370000 {
22 compatible = "rockchip,rk1808-mipi-dphy";
H A Drockchip,px30-dsi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
61 compatible = "rockchip,px30-dsi-dphy";
H A Dmixel,mipi-dsi-phy.txt9 - "fsl,imx8mq-mipi-dphy"
12 - "phy_ref": phandle and specifier referring to the DPHY ref clock
22 dphy: dphy@30a0030 {
23 compatible = "fsl,imx8mq-mipi-dphy";
H A Dallwinner,sun6i-a31-mipi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
19 - const: allwinner,sun6i-a31-mipi-dphy
21 - const: allwinner,sun50i-a64-mipi-dphy
22 - const: allwinner,sun6i-a31-mipi-dphy
53 compatible = "allwinner,sun6i-a31-mipi-dphy";
/OK3568_Linux_fs/kernel/drivers/media/platform/marvell-ccic/
H A Dmmp-driver.c51 * calc the dphy register values
52 * There are three dphy registers being used.
53 * dphy[0] - CSI2_DPHY3
54 * dphy[1] - CSI2_DPHY5
55 * dphy[2] - CSI2_DPHY6
73 * dphy[0] - CSI2_DPHY3: in mmpcam_calc_dphy()
75 * defines the time that the DPHY in mmpcam_calc_dphy()
99 pdata->dphy[0] = in mmpcam_calc_dphy()
107 pdata->dphy[0] = in mmpcam_calc_dphy()
129 * dphy[2] - CSI2_DPHY6: in mmpcam_calc_dphy()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip-mipi-csi-tx.c111 /* The table is based on 27MHz DPHY pll reference clock. */
319 if (csi->dphy.phy) in rockchip_mipi_dphy_power_on()
320 phy_power_on(csi->dphy.phy); in rockchip_mipi_dphy_power_on()
329 if (csi->dphy.phy) in rockchip_mipi_dphy_power_off()
330 phy_power_off(csi->dphy.phy); in rockchip_mipi_dphy_power_off()
337 /* enable csi tx, dphy and config lane num */ in rockchip_mipi_csi_tx_en()
361 /* disable csi tx, dphy and config lane num */ in rockchip_mipi_csi_host_power_off()
372 INPUT_DIVIDER(csi->dphy.input_div)); in rockchip_mipi_csi_phy_pll_init()
374 LOOP_DIV_LOW_SEL(csi->dphy.feedback_div) | in rockchip_mipi_csi_phy_pll_init()
379 LOOP_DIV_HIGH_SEL(csi->dphy.feedback_div) | in rockchip_mipi_csi_phy_pll_init()
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h1100 #define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */
1108 #define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */
1111 #define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */
1112 #define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */
1113 #define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */
1114 #define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */
1115 #define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */
1116 #define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */
1208 /* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */
1210 /* DPHY LP Receiver Enable */
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/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Ddw_mipi_dsi.c247 struct mipi_dphy dphy; member
472 if (dsi->dphy.phy) { in mipi_dphy_power_on()
473 rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_MIPI_DPHY); in mipi_dphy_power_on()
474 rockchip_phy_power_on(dsi->dphy.phy); in mipi_dphy_power_on()
537 n = dsi->dphy.input_div - 1; in dw_mipi_dsi_phy_init()
538 m = dsi->dphy.feedback_div - 1; in dw_mipi_dsi_phy_init()
638 dsi->dphy.input_div = best_prediv; in dw_mipi_dsi_set_pll()
639 dsi->dphy.feedback_div = best_fbdiv; in dw_mipi_dsi_set_pll()
642 dsi->slave->dphy.input_div = dsi->dphy.input_div; in dw_mipi_dsi_set_pll()
643 dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div; in dw_mipi_dsi_set_pll()
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/OK3568_Linux_fs/kernel/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c19 /* DPHY registers */
81 /* DPHY PLL parameters */
85 /* DPHY register values */
107 .name = "mipi-dphy",
117 dev_err(&phy->dev, "Failed to write DPHY reg %d: %d\n", reg, in phy_write()
391 dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret); in mixel_dphy_power_on()
425 { .compatible = "fsl,imx8mq-mipi-dphy",
460 dev_err(dev, "Couldn't create the DPHY regmap\n"); in mixel_dphy_probe()
489 .name = "mixel-mipi-dphy",
/OK3568_Linux_fs/kernel/drivers/staging/media/omap4iss/
H A Diss_csiphy.c94 reg = phy->dphy.ths_term << REGISTER0_THS_TERM_SHIFT; in csiphy_dphy_config()
95 reg |= phy->dphy.ths_settle << REGISTER0_THS_SETTLE_SHIFT; in csiphy_dphy_config()
100 reg = phy->dphy.tclk_term << REGISTER1_TCLK_TERM_SHIFT; in csiphy_dphy_config()
101 reg |= phy->dphy.tclk_miss << REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT; in csiphy_dphy_config()
102 reg |= phy->dphy.tclk_settle << REGISTER1_TCLK_SETTLE_SHIFT; in csiphy_dphy_config()
211 csi2->phy->dphy = csi2phy; in omap4iss_csiphy_config()
/OK3568_Linux_fs/kernel/drivers/staging/media/rkisp1/Documentation/devicetree/bindings/media/
H A Drockchip-isp1.yaml37 const: dphy
69 description: connection point for sensors at MIPI-DPHY RX0
136 phys = <&dphy>;
137 phy-names = "dphy";
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/bridge/
H A Dnwl-dsi.yaml63 A phandle to the phy module representing the DPHY
67 - const: dphy
193 phys = <&dphy>;
194 phy-names = "dphy";

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