Searched full:dmc0 (Results 1 – 7 of 7) sorted by relevance
72 ppmu_dmc0_3: ppmu-event3-dmc0 {73 event-name = "ppmu-event3-dmc0";76 ppmu_dmc0_2: ppmu-event2-dmc0 {77 event-name = "ppmu-event2-dmc0";80 ppmu_dmc0_1: ppmu-event1-dmc0 {81 event-name = "ppmu-event1-dmc0";84 ppmu_dmc0_0: ppmu-event0-dmc0 {85 event-name = "ppmu-event0-dmc0";163 ppmu_dmc0_3: ppmu-event3-dmc0 {164 event-name = "ppmu-event3-dmc0";
106 /* DRAM configuration (DMC0 and DMC1) */120 DMC0 = 0, enumerator202 if (ch == DMC0) { in s5pv210_set_refresh()282 s5pv210_set_refresh(DMC0, 83000); in s5pv210_target()458 * DMC0 : 166Mhz in s5pv210_target()461 s5pv210_set_refresh(DMC0, 166000); in s5pv210_target()465 * DMC0 : 83Mhz in s5pv210_target()468 s5pv210_set_refresh(DMC0, 83000); in s5pv210_target()
13 ppmu_dmc0_3: ppmu-event3-dmc0 {14 event-name = "ppmu-event3-dmc0";
28 dmc0 = &dmc0;513 dmc0: dmc@f0000000 { label
56 dmc0: dmc@200000 {
337 /* OneDRAM(DMC0) clock setting */
60 PPMU_EVENT(dmc0),