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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
12 - Guenter Roeck <groeck@chromium.org>
15 Google's ChromeOS EC is a microcontroller which talks to the AP and
17 The EC can be connected through various interfaces (I2C, SPI, and others)
23 - description:
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/i2c/
H A Dgoogle,cros-ec-i2c-tunnel.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/i2c/google,cros-ec-i2c-tunnel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: I2C bus that tunnels through the ChromeOS EC (cros-ec)
11 - Doug Anderson <dianders@chromium.org>
12 - Benson Leung <bleung@chromium.org>
13 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
16 On some ChromeOS board designs we've got a connection to the EC
18 other side of the EC (like a battery and PMIC). To get access to
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/extcon/
H A Dextcon-usbc-cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/extcon/extcon-usbc-cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC USB Type-C cable and accessories detection
10 - Benson Leung <bleung@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
17 The node for this device must be under a cros-ec node like google,cros-ec-spi
18 or google,cros-ec-i2c.
22 const: google,extcon-usbc-cros-ec
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pwm/
H A Dgoogle,cros-ec-pwm.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/google,cros-ec-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PWM controlled by ChromeOS EC
10 - Thierry Reding <thierry.reding@gmail.com>
11 - '"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>'
14 Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller
15 (EC) and controlled via a host-command interface.
16 An EC PWM node should be only found as a sub-node of the EC node (see
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dgoogle,cros-ec-codec.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/sound/google,cros-ec-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Audio codec controlled by ChromeOS EC
10 - Cheng-Yi Chiang <cychiang@chromium.org>
13 Google's ChromeOS EC codec is a digital mic codec provided by the
14 Embedded Controller (EC) and is controlled via a host-command
15 interface. An EC codec node should only be found inside the "codecs"
16 subnode of a cros-ec node.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/chrome/
H A Dgoogle,cros-ec-typec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Google Chrome OS EC(Embedded Controller) Type C port driver.
10 - Benson Leung <bleung@chromium.org>
11 - Prashant Malani <pmalani@chromium.org>
14 Chrome OS devices have an Embedded Controller(EC) which has access to
17 cros-ec node like google,cros-ec-spi.
21 const: google,cros-ec-typec
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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/misc/
H A Dcros-ec.txt8 - compatible = "google,cros-ec"
11 - spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus
13 - i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus
15 - ec-interrupt : Selects the EC interrupt, defined as a GPIO according
17 - optimise-flash-write : Boolean property - if present then flash blocks
18 containing all 0xff will not be written, since we assume that the EC
22 to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
29 spi@131b0000 {
30 cros-ec@0 {
32 compatible = "google,cros-ec";
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3288-veyron-chromebook.dtsi6 * SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/rockchip,rk808.h>
10 #include <dt-bindings/input/input.h>
11 #include "rk3288-veyron.dtsi"
20 gpio_keys: gpio-keys {
21 pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
26 linux,input-type = <5>; /* EV_SW */
27 debounce-interval = <1>;
28 gpio-key,wakeup;
32 gpio-charger {
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H A Dexynos5800-peach-pi.dts2 * SAMSUNG/GOOGLE Peach-Pit board device tree source
7 * SPDX-License-Identifier: GPL-2.0+
10 /dts-v1/;
15 cpu-model = "Exynos5800";
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
34 compatible = "pwm-backlight";
36 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
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H A Dexynos5420-peach-pit.dts2 * SAMSUNG/GOOGLE Peach-Pit board device tree source
7 * SPDX-License-Identifier: GPL-2.0+
10 /dts-v1/;
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
18 compatible = "google,pit-rev#", "google,pit",
22 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
23 hwid = "PIT TEST A-A 7848";
24 lazy-init = <1>;
35 compatible = "pwm-backlight";
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H A Dtegra124-nyan-big-u-boot.dtsi5 * SPDX-License-Identifier: GPL-2.0+
10 u-boot,dm-pre-reloc;
12 u-boot,dm-pre-reloc;
16 spi@7000d400 {
17 spi-deactivate-delay = <200>;
18 spi-max-frequency = <3000000>;
20 cros_ec: cros-ec@0 {
21 ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
H A Dexynos5250-snow.dts12 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/input/input.h>
32 spi0 = "/spi@12d20000";
33 spi1 = "/spi@12d30000";
34 spi2 = "/spi@12d40000";
35 spi3 = "/spi@131a0000";
36 spi4 = "/spi@131b0000";
52 stdout-path = "serial3:115200n8";
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H A Dtegra124-nyan.dtsi1 #include <dt-bindings/input/input.h>
19 vdd-supply = <&vdd_3v3_hdmi>;
20 pll-supply = <&vdd_hdmi_pll>;
21 hdmi-supply = <&vdd_5v0_hdmi>;
23 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
24 nvidia,hpd-gpio =
36 vdd-supply = <&vdd_3v3_panel>;
52 clock-frequency = <100000>;
54 acodec: audio-codec@10 {
57 interrupt-parent = <&gpio>;
[all …]
H A Dexynos5250-spring.dts7 * SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/input/input.h>
30 spi0 = "/spi@12d20000";
31 spi1 = "/spi@12d30000";
32 spi2 = "/spi@12d40000";
33 spi3 = "/spi@131a0000";
34 spi4 = "/spi@131b0000";
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/clock/rockchip,rk808.h>
10 #include <dt-bindings/input/input.h>
11 #include "rk3288-veyron.dtsi"
12 #include "rk3288-veyron-analog-audio.dtsi"
13 #include "rk3288-veyron-edp.dtsi"
14 #include "rk3288-veyron-sdmmc.dtsi"
22 gpio-charger {
23 compatible = "gpio-charger";
24 charger-type = "mains";
[all …]
H A Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
13 stdout-path = "serial0:115200n8";
19 * missing a unit-address. However, the bootloader on these Chromebook
21 * Adding the unit-address causes the bootloader to create a /memory
33 /delete-node/ memory@80000000;
39 vdd-supply = <&vdd_3v3_hdmi>;
40 pll-supply = <&vdd_hdmi_pll>;
41 hdmi-supply = <&vdd_5v0_hdmi>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/regulator/
H A Dgoogle,cros-ec-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/google,cros-ec-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC controlled voltage regulators
10 - Pi-Hsun Shih <pihsun@chromium.org>
17 - $ref: "regulator.yaml#"
21 const: google,cros-ec-regulator
25 description: Identifier for the voltage regulator to ChromeOS EC.
28 - compatible
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/OK3568_Linux_fs/kernel/drivers/platform/chrome/
H A Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
2 // SPI interface for ChromeOS Embedded Controller
14 #include <linux/spi/spi.h>
23 * Number of EC preamble bytes we read at a time. Since it takes
24 * about 400-500us for the EC to respond there is not a lot of
25 * point in tuning this. If the EC could respond faster then
28 * SPI transfer size is 256 bytes, so at 5MHz we need a response
34 * Allow for a long time for the EC to respond. We support i2c
50 * for this, clocking in at 2-3ms.
55 * Time between raising the SPI chip select (for the end of a
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
19 stdout-path = "serial0:115200n8";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
31 clock-output-names = "clk32k";
35 compatible = "regulator-fixed";
36 regulator-name = "it6505_pp18";
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 stdout-path = "serial2:115200n8";
23 * - Rails that only connect to the EC (or devices that the EC talks to)
25 * - Rails _are_ included if the rails go to the AP even if the AP
34 * - The EC controls the enable and the EC always enables a rail as
36 * - The rails are actually connected to each other by a jumper and
41 ppvar_sys: ppvar-sys {
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 /delete-node/ &hyp_mem;
24 /delete-node/ &xbl_mem;
25 /delete-node/ &aop_mem;
26 /delete-node/ &sec_apps_mem;
27 /delete-node/ &tz_mem;
35 reserved-memory {
[all …]
H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
26 stdout-path = "serial0:115200n8";
30 compatible = "pwm-backlight";
32 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
33 power-supply = <&ppvar_sys>;
34 pinctrl-names = "default";
35 pinctrl-0 = <&ap_edp_bklten>;
[all …]
/OK3568_Linux_fs/u-boot/arch/sandbox/dts/
H A Dsandbox.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
18 stdout-path = "/serial";
21 cros_ec: cros-ec@0 {
23 compatible = "google,cros-ec-sandbox";
26 * This describes the flash memory within the EC. Note
29 #address-cells = <1>;
30 #size-cells = <1>;
33 erase-value = <0>;
[all …]
/OK3568_Linux_fs/kernel/include/linux/platform_data/
H A Dcros_ec_proto.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * The EC is unresponsive for a time after a reboot command. Add a
31 * Max bus-specific overhead incurred by request/responses.
34 * SPI requires up to 32 additional bytes for responses.
41 * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
58 * struct cros_ec_command - Information about a ChromeOS EC command.
62 * @insize: Max number of bytes to accept from the EC.
63 * @result: EC's response to the command (separate from communication failure).
64 * @data: Where to put the incoming data from EC and outgoing data to EC.
76 * struct cros_ec_device - Information about a ChromeOS EC device.
[all …]
/OK3568_Linux_fs/u-boot/drivers/misc/
H A Dcros_ec.c6 * SPDX-License-Identifier: GPL-2.0+
10 * This is the interface to the Chrome OS EC. It provides keyboard functions,
12 * provided to enable the EC software to be updated, talk to the EC's I2C bus
13 * and store a small amount of data in a memory which persists while the EC
24 #include <spi.h>
27 #include <asm-generic/gpio.h>
28 #include <dm/device-internal.h>
30 #include <dm/uclass-internal.h>
53 if (cmd != -1) in cros_ec_dump_data()
62 * Calculate a simple 8-bit checksum of a data block
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