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Searched full:crg_ctrl (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/hisilicon/
H A Dhi3660.dtsi339 crg_ctrl: crg_ctrl@fff35000 { label
348 hisi,rst-syscon = <&crg_ctrl>;
358 pmuctrl: crg_ctrl@fff34000 {
403 clocks = <&crg_ctrl HI3660_OSC32K>,
404 <&crg_ctrl HI3660_OSC32K>,
405 <&crg_ctrl HI3660_OSC32K>;
416 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
430 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
444 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
458 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
[all …]
H A Dhi3670.dtsi148 crg_ctrl: crg_ctrl@fff35000 { label
158 hisi,rst-syscon = <&crg_ctrl>;
167 pmuctrl: crg_ctrl@fff34000 {
201 clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
202 <&crg_ctrl HI3670_PCLK>;
213 clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
214 <&crg_ctrl HI3670_PCLK>;
224 clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
225 <&crg_ctrl HI3670_PCLK>;
236 clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
[all …]
H A Dhi3660-drm.dtsi14 clocks = <&crg_ctrl HI3660_ACLK_GATE_DSS>,
15 <&crg_ctrl HI3660_PCLK_GATE_DSS>,
16 <&crg_ctrl HI3660_CLK_GATE_EDC0>,
17 <&crg_ctrl HI3660_CLK_GATE_LDI0>,
18 <&crg_ctrl HI3660_CLK_GATE_LDI1>,
50 clocks = <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_REF>,
51 <&crg_ctrl HI3660_CLK_GATE_TXDPHY1_REF>,
52 <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_CFG>,
53 <&crg_ctrl HI3660_CLK_GATE_TXDPHY1_CFG>,
54 <&crg_ctrl HI3660_PCLK_GATE_DSI0>,
[all …]
H A Dhi3660-coresight.dtsi17 clocks = <&crg_ctrl HI3660_PCLK>;
34 clocks = <&crg_ctrl HI3660_PCLK>;
51 clocks = <&crg_ctrl HI3660_PCLK>;
68 clocks = <&crg_ctrl HI3660_PCLK>;
85 clocks = <&crg_ctrl HI3660_PCLK>;
134 clocks = <&crg_ctrl HI3660_PCLK>;
160 clocks = <&crg_ctrl HI3660_PCLK>;
177 clocks = <&crg_ctrl HI3660_PCLK>;
194 clocks = <&crg_ctrl HI3660_PCLK>;
211 clocks = <&crg_ctrl HI3660_PCLK>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dkirin-pcie.txt42 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
43 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
44 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
45 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
46 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dhi3670-clock.txt30 crg_ctrl: clock-controller@fff35000 {
40 clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
41 <&crg_ctrl HI3670_PCLK>;
H A Dhi3660-clock.txt34 crg_ctrl: clock-controller@fff35000 {
44 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
45 <&crg_ctrl HI3660_PCLK>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pwm/
H A Dpwm-hibvt.txt20 clocks = <&crg_ctrl HI3516CV300_PWM_CLK>;
21 resets = <&crg_ctrl 0x38 0>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/ufs/
H A Dufs-hisi.txt35 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
36 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dhisilicon,hi3660-usb3.yaml55 hisilicon,pericrg-syscon = <&crg_ctrl>;
/OK3568_Linux_fs/kernel/drivers/staging/hikey9xx/
H A Dphy-hi3670-usb3.yaml65 hisilicon,pericrg-syscon = <&crg_ctrl>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dcoresight.txt252 clocks = <&crg_ctrl HI3660_PCLK>;