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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
27 - Running
28 - Idle_standby
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H A Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/hisilicon/
H A Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a57";
30 cpu-idle-states = <&CPU_PW20>;
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/OK3568_Linux_fs/kernel/Documentation/translations/zh_CN/arm64/
H A Dsilicon-errata.txt1 Chinese translated version of Documentation/arm64/silicon-errata.rst
12 ---------------------------------------------------------------------
13 Documentation/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/arm64/
H A Dmapfile.csv10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd030,v1,arm/cortex-a53,core
16 0x00000000420f1000,v1,arm/cortex-a53,core
17 0x00000000410fd070,v1,arm/cortex-a57-a72,core
18 0x00000000410fd080,v1,arm/cortex-a57-a72,core
19 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
20 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
/OK3568_Linux_fs/yocto/poky/meta/conf/machine/include/arm/armv8a/
H A Dtune-cortexa57-cortexa53.inc1 DEFAULTTUNE ?= "cortexa57-cortexa53"
3 TUNEVALID[cortexa57-cortexa53] = "Enable big.LITTLE Cortex-A57.Cortex-A53 specific processor optimi…
4 …ARGS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa57-cortexa53", " -mcpu=cortex-a57.cortex-a5…
5 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa57-cortexa53", "cortexa57-cortex…
7 require conf/machine/include/arm/arch-armv8a.inc
10 AVAILTUNES += "cortexa57-cortexa53"
11 ARMPKGARCH:tune-cortexa57-cortexa53 = "cortexa57-cortexa53"
12 TUNE_FEATURES:tune-cortexa57-cortexa53 = "${TUNE_FEATURES:tune-armv8a-crc} cortexa57-cortexa53"
13 PACKAGE_EXTRA_ARCHS:tune-cortexa57-cortexa53 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa57-co…
14 BASE_LIB:tune-cortexa57-cortexa53 = "lib64"
H A Dtune-cortexa57.inc3 TUNEVALID[cortexa57] = "Enable Cortex-A57 specific processor optimizations"
4 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa57', ' -mcpu=cortex-a57', '', d)}"
6 require conf/machine/include/arm/arch-armv8a.inc
9 AVAILTUNES += "cortexa57 cortexa57-crypto"
10 ARMPKGARCH:tune-cortexa57 = "cortexa57"
11 ARMPKGARCH:tune-cortexa57-crypto = "cortexa57-crypto"
12 TUNE_FEATURES:tune-cortexa57 = "${TUNE_FEATURES:tune-armv8a-crc} cortexa57"
13 TUNE_FEATURES:tune-cortexa57-crypto = "${TUNE_FEATURES:tune-cortexa57} crypto"
14 PACKAGE_EXTRA_ARCHS:tune-cortexa57 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa57"
15 PACKAGE_EXTRA_ARCHS:tune-cortexa57-crypto = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc-crypto} cor…
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/arm/
H A Djuno.dts4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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H A Djuno-r1.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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/OK3568_Linux_fs/buildroot/arch/
H A DConfig.in.arm146 bool "arm1136j-s"
152 bool "arm1136jf-s"
159 bool "arm1176jz-s"
165 bool "arm1176jzf-s"
181 bool "cortex-A5"
189 bool "cortex-A7"
197 bool "cortex-A8"
205 bool "cortex-A9"
213 bool "cortex-A12"
221 bool "cortex-A15"
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amazon/
H A Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
105 combination of Denver and Cortex-A57 CPU cores and a GPU based on
106 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
108 multi-format support, ISP for image capture processing and BPMP for
/OK3568_Linux_fs/kernel/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
168 if $(cc-option,-fpatchable-function-entry=2)
217 ARM 64-bit (AArch64) Linux support.
249 # VA_BITS - PAGE_SHIFT - 3
342 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
369 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
374 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
377 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
383 data cache clean-and-invalidate.
391 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
25 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc11 ---------
12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
24 - Packet parsing, classification, and distribution (FMan)
25 - Queue management for scheduling, packet sequencing, and congestion
27 - Hardware buffer management for buffer allocation and de-allocation (BMan)
28 - Cryptography acceleration (SEC)
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dmsm8994.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
9 interrupt-parent = <&intc>;
11 #address-cells = <2>;
12 #size-cells = <2>;
17 xo_board: xo-board {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/lib/gcc/aarch64-none-linux-gnu/10.3.1/plugin/include/config/aarch64/
H A Daarch64-cores.def1 /* Copyright (C) 2011-2020 Free Software Foundation, Inc.
31 aarch64-arches.def.
32 FLAGS are the bitwise-or of the traits that apply to that core.
38 ARMv8-A architecture profile.
44 in /proc/cpuinfo. If this is -1, this means it can match any variant. */
46 /* ARMv8-A Architecture Processors. */
49 AARCH64_CORE("cortex-a34", cortexa34, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, corte…
50 AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, corte…
51 AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, corte…
52 AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, corte…
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A DKconfig12 Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
28 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
29 Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
37 Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
38 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
167 default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
/OK3568_Linux_fs/kernel/Documentation/arm64/
H A Dsilicon-errata.rst10 so-called "errata", which can cause it to deviate from the architecture
32 cases (e.g. those cases that both require a non-secure workaround *and*
37 Features" -> "ARM errata workarounds via the alternatives framework".
39 CPU is detected. For less-intrusive workarounds, a Kconfig option is not
49 +----------------+-----------------+-----------------+-----------------------------+
53 +----------------+-----------------+-----------------+-----------------------------+
54 +----------------+-----------------+-----------------+-----------------------------+
55 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
56 +----------------+-----------------+-----------------+-----------------------------+
57 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
[all …]
/OK3568_Linux_fs/yocto/poky/meta/recipes-devtools/gcc/gcc/
H A D0001-aarch64-Update-Neoverse-N2-core-defini.patch10 * config/aarch64/aarch64-cores.def: Update Neoverse N2 core entry.
12 Upstream-Status: Backport
13 Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
14 ---
15 gcc/config/aarch64/aarch64-cores.def | 6 +++---
16 1 file changed, 3 insertions(+), 3 deletions(-)
18 diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
20 --- a/gcc/config/aarch64/aarch64-cores.def
21 +++ b/gcc/config/aarch64/aarch64-cores.def
22 @@ -145,9 +145,6 @@ AARCH64_CORE("neoverse-512tvb", neoverse512tvb, cortexa57, 8_4A, AARCH64_FL_FOR
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