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/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
7 tristate "Rockchip CSI2 D-PHY Driver"
16 tristate "Rockchip Display Port PHY Driver"
20 Enable this to support the Rockchip Display Port PHY.
32 will be called phy-rockchip-dphy-rx0.
35 tristate "Rockchip EMMC PHY Driver"
39 Enable this to support the Rockchip EMMC PHY.
50 tristate "Rockchip INNO HDMI PHY Driver"
55 Enable this to support the Rockchip Innosilicon HDMI PHY.
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/OK3568_Linux_fs/u-boot/drivers/phy/
H A DKconfig2 menu "PHY Subsystem"
4 config PHY config
5 bool "PHY Core"
8 PHY support.
10 This framework is designed to provide a generic interface for PHY
11 devices. PHY devices are dedicated hardware that handle the physical
13 PHYs are commonly used for high speed interfaces such as Serial-ATA
16 PHY, power on/off the PHY, and reset the PHY. It's meant to be as
21 bool "PHY Core in SPL"
24 PHY support in SPL.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dbrcm,stingray-usb-phy.txt1 Broadcom Stingray USB PHY
4 - compatible : should be one of the listed compatibles
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
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H A Dintel,combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
14 controllers. A single Combophy provides two PHY instances.
18 pattern: "combophy(@.*|-[0-9a-f])*$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
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H A Dphy-rockchip-naneng-combphy.txt1 ROCKCHIP COMBO PHY WITH NANENG IP BLOCK
3 Required properties (phy (parent) node):
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3568-naneng-combphy"
6 - reg : the address offset of grf for combo-phy configuration.
7 - rockchip,pipe-grf : phandle to the syscon managing the "pipe general register files"
8 - rockchip,pipe-phy-grf: phandle to the syscon managing the "phy general register files"
9 - clocks : phandle + phy specifier pair, for the input clocks of phy.
10 - clock-names : input clocks name of phy.
11 - resets : phandle + reset specifier pairs.
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H A Damlogic,meson-g12a-usb3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <narmstrong@baylibre.com>
16 - amlogic,meson-g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
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H A Dphy-rockchip-inno-video-combo-phy.txt1 ROCKCHIP MIPI/LVDS/TTL VIDEO COMBO PHY WITH INNO IP BLOCK
4 - compatible : must be one of:
5 "rockchip,px30-video-phy",
6 "rockchip,rk3128-video-phy",
7 "rockchip,rk3368-video-phy";
8 "rockchip,rk3568-video-phy";
9 - reg : the address offset of register for phy and host configuration.
10 - #phy-cells : must be 0. See ./phy-bindings.txt for details.
11 - clocks: must include clock specifiers corresponding to entries in the
12 clock-names property. See ../clocks/clock-bindings.txt for details.
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H A Dcalxeda-combophy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 not by a dedicated PHY driver.
18 - Andre Przywara <andre.przywara@arm.com>
22 const: calxeda,hb-combophy
24 '#phy-cells':
36 - compatible
37 - reg
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H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USBDP Combo PHY with Samsung IP block
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3588-usbdp-phy
23 - description: phy ref clock.
24 - description: phy pcs immortal clock.
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_combo_phy.c1 // SPDX-License-Identifier: MIT
14 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
41 * CNL has just one set of registers, while gen11 has a set for each combo PHY.
42 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in cnl_get_procmon_ref_values() argument
51 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in cnl_get_procmon_ref_values()
77 enum phy phy) in cnl_set_procmon_ref_values() argument
82 procmon = cnl_get_procmon_ref_values(dev_priv, phy); in cnl_set_procmon_ref_values()
84 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in cnl_set_procmon_ref_values()
86 val |= procmon->dw1; in cnl_set_procmon_ref_values()
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H A Dintel_dpll_mgr.h2 * Copyright © 2012-2016 Intel Corporation
38 __a > __b ? (__a - __b) : (__b - __a); })
49 * enum intel_dpll_id - possible DPLL ids
55 * @DPLL_ID_PRIVATE: non-shared dpll in use
57 DPLL_ID_PRIVATE = -1,
114 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
118 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
122 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
216 * struct intel_shared_dpll_state - hold the DPLL atomic state
239 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dhisilicon,histb-xhci.txt6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
20 - phys: a list of phandle + phy specifier pairs
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/OK3568_Linux_fs/kernel/drivers/phy/amlogic/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Amlogic platforms
6 tristate "Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY driver"
19 tristate "Meson GXL and GXM USB2 PHY drivers"
31 tristate "Meson G12A USB2 PHY driver"
42 tristate "Meson G12A USB3+PCIE Combo PHY driver"
48 Enable this to support the Meson USB3 + PCIE Combo PHY found
53 tristate "Meson AXG PCIE PHY driver"
59 Enable this to support the Meson MIPI + PCIE PHY found
64 tristate "Meson AXG MIPI + PCIE analog PHY driver"
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H A Dphy-meson-g12a-usb3-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic G12A USB3 + PCIE Combo PHY driver
15 #include <linux/phy/phy.h>
19 #include <dt-bindings/phy/phy.h>
60 struct phy *phy; member
79 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
80 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
82 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); in phy_g12a_usb3_pcie_cr_bus_addr()
84 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, in phy_g12a_usb3_pcie_cr_bus_addr()
90 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
13 * to 40-bit
15 dma-ranges = <0 0 0 0 0x100 0x0>;
17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
20 #phy-cells = <1>;
25 compatible = "generic-xhci";
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H A Dbcm958742k.dts4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 /dts-v1/;
35 #include "bcm958742-base.dtsi"
39 model = "Stingray Combo SVK (BCM958742K)";
43 enet-phy-lane-swap;
47 mmc-ddr-1_8v;
59 pinctrl-0 = <&spi0_pins>;
60 pinctrl-names = "default";
61 cs-gpios = <&gpio_hsls 34 0>;
64 spi-flash@0 {
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/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A DKconfig5 select PHY
7 Rockchip SoCs provide video output capabilities for High-Definition
8 Multimedia Interface (HDMI), Low-voltage Differential Signalling
11 This driver supports the on-chip video output device, and targets the
37 Driver for Maxim MAX96755F GMSL2 Serializer with MIPI-DSI Input.
40 bool "Rohm BU18RL82-based panels"
47 bool "Maxim MAX96752F-based panels"
89 bool "Rockchip specific extensions for INNO HDMI PHY"
92 This selects support for INNO HDMI PHY. If you want to
97 tristate "Rockchip INNO MIPI PHY driver"
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/OK3568_Linux_fs/kernel/drivers/phy/intel/
H A Dphy-intel-lgm-combo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
15 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
80 struct phy *phy; member
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_INTEL_KEEMBAY_EMMC) += phy-intel-keembay-emmc.o
3 obj-$(CONFIG_PHY_INTEL_LGM_COMBO) += phy-intel-lgm-combo.o
4 obj-$(CONFIG_PHY_INTEL_LGM_EMMC) += phy-intel-lgm-emmc.o
/OK3568_Linux_fs/kernel/drivers/phy/allwinner/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Allwinner platforms
6 tristate "Allwinner sunxi SoC USB PHY driver"
19 This driver controls the entire USB PHY block, both the USB OTG
23 tristate "Allwinner A31 MIPI D-PHY Support"
32 MIPI-DSI support. If M is selected, the module will be
36 tristate "Allwinner sun9i SoC USB PHY driver"
47 This driver controls each individual USB 2 host PHY.
50 tristate "Allwinner H6 SoC USB3 PHY driver"
56 Enable this to support the USB3.0-capable transceiver that is
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Decx-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
20 #address-cells = <1>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
23 interrupt-parent = <&intc>;
26 compatible = "calxeda,hb-ahci";
29 dma-coherent;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
33 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
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/OK3568_Linux_fs/u-boot/include/linux/usb/
H A Dphy-rockchip-usbdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
13 /* RK3588 USBDP PHY Register Definitions */
/OK3568_Linux_fs/kernel/include/linux/phy/
H A Dphy-rockchip-usbdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
13 /* RK3588 USBDP PHY Register Definitions */
/OK3568_Linux_fs/kernel/drivers/phy/broadcom/
H A Dphy-bcm-sr-usb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
11 #include <linux/phy/phy.h>
25 /* USB PHY registers */
88 struct phy *phy; member
127 void __iomem *regs = phy_cfg->regs; in bcm_usb_ss_phy_init()
131 offset = phy_cfg->offset; in bcm_usb_ss_phy_init()
158 void __iomem *regs = phy_cfg->regs; in bcm_usb_hs_phy_init()
161 offset = phy_cfg->offset; in bcm_usb_hs_phy_init()
174 static int bcm_usb_phy_reset(struct phy *phy) in bcm_usb_phy_reset() argument
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/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Dbcm-cygnus.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "bcm-phy-lib.h"
11 #include <linux/phy.h>
17 /* Broadcom Cygnus Phy specific registers */
97 /* Apply AFE settings for the PHY */ in bcm_cygnus_config_init()
117 /* Re-initialize the PHY to apply AFE work-arounds and in bcm_cygnus_resume()
133 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm_omega_config_init()
135 pr_info_once("%s: %s PHY revision: 0x%02x\n", in bcm_omega_config_init()
136 phydev_name(phydev), phydev->drv->name, rev); in bcm_omega_config_init()
172 /* Re-apply workarounds coming out suspend/resume */ in bcm_omega_resume()
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