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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-gates-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Bus Gates Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 This additional argument passed to that clock is the offset of
24 - const: allwinner,sun4i-a10-gates-clk
[all …]
H A Drenesas,cpg-mstp-clocks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
18 and the clock index in the group, from 0 to 31.
23 - enum:
24 - renesas,r7s72100-mstp-clocks # RZ/A1
[all …]
H A Dallwinner,sun8i-h3-bus-gates-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Bus Gates Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 This additional argument passed to that clock is the offset of
23 const: allwinner,sun8i-h3-bus-gates-clk
[all …]
H A Dclock-bindings.txt1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Darm,scpi.txt2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
26 Clock bindings for the clocks based on SCPI Message Protocol
27 ------------------------------------------------------------
29 This binding uses the common clock binding[1].
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dr7s72100.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 #include <dt-bindings/clock/r7s72100-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
[all …]
H A Ddm816x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
[all …]
H A Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
H A Dsh73a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
H A Dr8a7778.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Ddm816x-clocks.dtsi9 #clock-cells = <1>;
10 compatible = "ti,dm816-fapll-clock";
13 clock-indices = <1>, <2>, <3>, <4>, <5>,
15 clock-output-names = "main_pll_clk1",
25 #clock-cells = <1>;
26 compatible = "ti,dm816-fapll-clock";
29 clock-indices = <1>, <2>, <3>, <4>;
30 clock-output-names = "ddr_pll_clk1",
37 #clock-cells = <1>;
38 compatible = "ti,dm816-fapll-clock";
[all …]
H A Dsun5i-a13.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
50 #include <dt-bindings/thermal/thermal.h>
53 interrupt-parent = <&intc>;
56 #address-cells = <1>;
57 #size-cells = <1>;
61 compatible = "allwinner,simple-framebuffer",
62 "simple-framebuffer";
63 allwinner,pipeline = "de_be0-lcd0";
[all …]
H A Dsun5i-a10s.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&intc>;
60 #address-cells = <1>;
61 #size-cells = <1>;
65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
[all …]
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 interrupt-parent = <&gic>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a7";
65 compatible = "arm,cortex-a7";
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sun8i-bus-gates.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on clk-simple-gates.c, which is:
8 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/clk-provider.h>
41 int idx = of_property_match_string(node, "clock-names", in sun8i_h3_bus_gates_init()
53 number = of_property_count_u32_elems(node, "clock-indices"); in sun8i_h3_bus_gates_init()
54 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sun8i_h3_bus_gates_init()
56 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sun8i_h3_bus_gates_init()
57 if (!clk_data->clks) in sun8i_h3_bus_gates_init()
61 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sun8i_h3_bus_gates_init()
[all …]
H A Dclk-simple-gates.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
9 #include <linux/clk-provider.h>
43 number = of_property_count_u32_elems(node, "clock-indices"); in sunxi_simple_gates_setup()
44 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sunxi_simple_gates_setup()
46 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sunxi_simple_gates_setup()
47 if (!clk_data->clks) in sunxi_simple_gates_setup()
50 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sunxi_simple_gates_setup()
51 of_property_read_string_index(node, "clock-output-names", in sunxi_simple_gates_setup()
57 clk_data->clks[index] = clk_register_gate(NULL, clk_name, in sunxi_simple_gates_setup()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/
H A Ddhd_bus.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Header file describing the internal (inter-module) DHD interfaces.
8 * Copyright (C) 1999-2017, Broadcom Corporation
29 * <<Broadcom-WL-IPTag/Open:>>
31 * $Id: dhd_bus.h 698895 2017-05-11 02:55:17Z $
109 /* Check for and handle local prot-specific iovar commands */
130 /* Set user-specified nvram parameters. */
146 (_bus)->dhd->busstate = DHD_BUS_DOWN; \
168 /* DMA Indices array buffers for: H2D WR and RD, and D2H WR and RD */
169 H2D_DMA_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Dclk-mstp.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
25 * status register when enabling the clock.
31 * struct mstp_clock_group - MSTP gating clocks group
33 * @data: clock specifier translation for clocks in this group
37 * @width_8bit: registers are 8-bit, not 32-bit
50 * struct mstp_clock - MSTP gating clock
51 * @hw: handle between common and hardware-specific interfaces
66 return group->width_8bit ? readb(reg) : readl(reg); in cpg_mstp_read()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/serial/
H A Dnxp,sc16is7xx.txt1 * NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
5 - compatible: Should be one of the following:
6 - "nxp,sc16is740" for NXP SC16IS740,
7 - "nxp,sc16is741" for NXP SC16IS741,
8 - "nxp,sc16is750" for NXP SC16IS750,
9 - "nxp,sc16is752" for NXP SC16IS752,
10 - "nxp,sc16is760" for NXP SC16IS760,
11 - "nxp,sc16is762" for NXP SC16IS762.
12 - reg: I2C address of the SC16IS7xx device.
13 - interrupts: Should contain the UART interrupt
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/
H A Ddhd_bus.h2 * Header file describing the internal (inter-module) DHD interfaces.
9 * Copyright (C) 1999-2017, Broadcom Corporation
30 * <<Broadcom-WL-IPTag/Open:>>
32 * $Id: dhd_bus.h 701741 2017-05-26 08:18:08Z $
101 /* Check for and handle local prot-specific iovar commands */
117 /* Set user-specified nvram parameters. */
133 (_bus)->dhd->busstate = DHD_BUS_DOWN; \
157 /* DMA Indices array buffers for: H2D WR and RD, and D2H WR and RD */
158 H2D_DMA_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
159 H2D_DMA_INDX_RD_BUF, /* update H2D RD dma indices buf base addr to dongle */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/
H A Ddhd_bus.h2 * Header file describing the internal (inter-module) DHD interfaces.
9 * Copyright (C) 1999-2017, Broadcom Corporation
30 * <<Broadcom-WL-IPTag/Open:>>
32 * $Id: dhd_bus.h 701741 2017-05-26 08:18:08Z $
101 /* Check for and handle local prot-specific iovar commands */
117 /* Set user-specified nvram parameters. */
133 (_bus)->dhd->busstate = DHD_BUS_DOWN; \
157 /* DMA Indices array buffers for: H2D WR and RD, and D2H WR and RD */
158 H2D_DMA_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
159 H2D_DMA_INDX_RD_BUF, /* update H2D RD dma indices buf base addr to dongle */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/infineon/
H A Ddhd_bus.h2 * Header file describing the internal (inter-module) DHD interfaces.
9 * Copyright (C) 1999-2017, Broadcom Corporation
30 * <<Broadcom-WL-IPTag/Open:>>
32 * $Id: dhd_bus.h 701741 2017-05-26 08:18:08Z $
101 /* Check for and handle local prot-specific iovar commands */
117 /* Set user-specified nvram parameters. */
133 (_bus)->dhd->busstate = DHD_BUS_DOWN; \
157 /* DMA Indices array buffers for: H2D WR and RD, and D2H WR and RD */
158 H2D_DMA_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
159 H2D_DMA_INDX_RD_BUF, /* update H2D RD dma indices buf base addr to dongle */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/
H A Ddhd_bus.h2 * Header file describing the internal (inter-module) DHD interfaces.
24 * <<Broadcom-WL-IPTag/Open:>>
106 /* Check for and handle local prot-specific iovar commands */
122 /* Set user-specified nvram parameters. */
138 (_bus)->dhd->busstate = DHD_BUS_DOWN; \
162 /* DMA Indices array buffers for: H2D WR and RD, and D2H WR and RD */
163 H2D_DMA_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
164 H2D_DMA_INDX_RD_BUF, /* update H2D RD dma indices buf base addr to dongle */
165 D2H_DMA_INDX_WR_BUF, /* update D2H WR dma indices buf base addr to dongle */
166 D2H_DMA_INDX_RD_BUF, /* update D2H RD dma indices buf base addr to dongle */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/
H A Ddhd_bus.h2 * Header file describing the internal (inter-module) DHD interfaces.
24 * <<Broadcom-WL-IPTag/Open:>>
108 /* Check for and handle local prot-specific iovar commands */
124 /* Set user-specified nvram parameters. */
140 (_bus)->dhd->busstate = DHD_BUS_DOWN; \
164 /* DMA Indices array buffers for: H2D WR and RD, and D2H WR and RD */
165 H2D_DMA_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
166 H2D_DMA_INDX_RD_BUF, /* update H2D RD dma indices buf base addr to dongle */
167 D2H_DMA_INDX_WR_BUF, /* update D2H WR dma indices buf base addr to dongle */
168 D2H_DMA_INDX_RD_BUF, /* update D2H RD dma indices buf base addr to dongle */
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/clock/
H A Dmicrochip,pic32-clock.txt1 * Microchip PIC32 Clock and Oscillator
3 Microchip PIC32 clock tree consists of few oscillators, PLLs,
5 to various controllers within SoC and also to off-chip.
7 PIC32 clock controller output is defined by indices as defined
10 [0] include/dt-bindings/clock/microchip,clock.h
13 - compatible: should be "microchip,pic32mzda_clk"
14 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
18 Example: Clock controller node:
20 clock: clk@1f801200 {
[all …]

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