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/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A Dclk-iproc-asiu.c16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
32 struct iproc_asiu_div div; member
48 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_enable() local
49 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable()
53 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
56 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
57 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
58 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
65 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_disable() local
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/spear/
H A Dspear1340_clock.c2 * arch/arm/mach-spear13xx/spear1340_clock.c
19 #include "clk.h"
178 /* vco-pll4 rate configuration table, in ascending order of rates */
191 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
192 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
193 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
194 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
195 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
196 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
208 * --------------------------------------------------------------------
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Dclk-regmap.c1 // SPDX-License-Identifier: GPL-2.0
8 #include "clk-regmap.h"
12 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_endisable() local
13 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_endisable()
14 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_regmap_gate_endisable()
18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
34 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_is_enabled() local
35 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); in clk_regmap_gate_is_enabled()
38 regmap_read(clk->map, gate->offset, &val); in clk_regmap_gate_is_enabled()
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/OK3568_Linux_fs/kernel/arch/c6x/platforms/
H A Dplldata.c1 // SPDX-License-Identifier: GPL-2.0-only
27 struct clk clkin1 = {
127 struct clk c6x_core_clk = {
132 struct clk c6x_i2c_clk = {
136 struct clk c6x_watchdog_clk = {
140 struct clk c6x_mcbsp1_clk = {
144 struct clk c6x_mcbsp2_clk = {
148 struct clk c6x_mdio_clk = {
155 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
156 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
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/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3308.c4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rk3308-cru.h>
29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
89 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
139 struct rk3308_cru *cru = priv->cru; in rk3308_armclk_set_clk()
146 return -EINVAL; in rk3308_armclk_set_clk()
155 priv->cru, APLL); in rk3308_armclk_set_clk()
158 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
159 return -EINVAL; in rk3308_armclk_set_clk()
[all …]
H A Dclk_rk3562.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
8 #include <clk-uclass.h>
16 #include <dt-bindings/clock/rk3562-cru.h>
20 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
105 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
156 struct rk3562_cru *cru = priv->cru; in rk3562_armclk_set_rate()
162 return -EINVAL; in rk3562_armclk_set_rate()
168 old_rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru, in rk3562_armclk_set_rate()
171 rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK, in rk3562_armclk_set_rate()
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H A Dclk_rk3368.c3 * Author: Andy Yan <andy.yan@rock-chips.com>
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3368-cru.h>
62 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
121 static ulong rk3368_clk_get_rate(struct clk *clk);
141 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config() argument
154 return -EINVAL; in pll_para_config()
165 div->nr = best_div->nr; in pll_para_config()
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H A Dclk_rk3588.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
9 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rk3588-cru.h>
22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
101 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
152 struct rk3588_cru *cru = priv->cru; in rk3588_center_get_clk()
157 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
170 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
183 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
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H A Dclk_rk3328.c4 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
19 #include <dt-bindings/clock/rk3328-cru.h>
24 ((input_rate) / (output_rate) - 1);
25 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
120 struct rk3328_cru *cru = priv->cru; in rk3328_armclk_set_clk()
127 return -EINVAL; in rk3328_armclk_set_clk()
136 priv->cru, NPLL); in rk3328_armclk_set_clk()
139 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
140 return -EINVAL; in rk3328_armclk_set_clk()
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H A Dclk_rk3288.c4 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
108 /* CLKSEL1: pd bus clk pll sel: codec or general */
114 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
118 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
122 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
[all …]
H A Dclk_rv1126.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
9 #include <clk-uclass.h>
19 #include <dt-bindings/clock/rv1126-cru.h>
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
103 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
154 priv->pmucru, GPLL); in rv1126_gpll_get_pmuclk()
174 return -EINVAL; in rv1126_gpll_set_pmuclk()
181 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_rtc32k_get_pmuclk()
185 fracdiv = readl(&pmucru->pmu_clksel_con[13]); in rv1126_rtc32k_get_pmuclk()
[all …]
H A Dclk_rk1808.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
12 #include <clk.h>
18 #include <dt-bindings/clock/rk1808-cru.h>
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
97 struct rk1808_cru *cru = priv->cru; in rk1808_i2c_get_clk()
98 u32 div, con; in rk1808_i2c_get_clk() local
102 con = readl(&cru->pmu_clksel_con[7]); in rk1808_i2c_get_clk()
103 div = (con & CLK_I2C0_DIV_CON_MASK) >> CLK_I2C0_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
106 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
[all …]
H A Dclk_px30.c4 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
19 #include <dt-bindings/clock/px30-cru.h>
51 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
139 rate->postdiv1 = postdiv1; in pll_clk_set_by_auto()
140 rate->postdiv2 = postdiv2; in pll_clk_set_by_auto()
149 diff_khz = vco_khz - fbdiv * fref_khz; in pll_clk_set_by_auto()
152 diff_khz = fref_khz - diff_khz; in pll_clk_set_by_auto()
159 rate->refdiv = refdiv; in pll_clk_set_by_auto()
160 rate->fbdiv = fbdiv; in pll_clk_set_by_auto()
[all …]
H A Dclk_rk3528.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Joseph Chen <chenjh@rock-chips.com>
8 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3528-cru.h>
21 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
27 * - frac mode: refdiv can be 1 or 2 only
28 * - int mode: refdiv has no special limit
29 * - VCO range: [950, 3800] MHZ
32 * - int mode: refdiv can be 1 or 2 only
33 * - VCO range: [475, 1900] MHZ
[all …]
H A Dclk_rk322x.c4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3228-cru.h>
22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
94 struct rk322x_cru *cru = priv->cru; in rk322x_armclk_set_clk()
101 return -EINVAL; in rk322x_armclk_set_clk()
110 priv->cru, APLL); in rk322x_armclk_set_clk()
113 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
114 return -EINVAL; in rk322x_armclk_set_clk()
115 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_armclk_set_clk()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
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H A Dclk-sun9i-cpus.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
22 * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
36 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
37 (div << SUN9I_CPUS_DIV_SHIFT))
42 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
43 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
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/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * samsung/clk.c
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
25 #include "clk.h"
31 * src1 --|--\
32 * |M |--[GATE]-[DIV]-
33 * src2 --|--/
37 static struct clk *rockchip_clk_register_branch(const char *name, in rockchip_clk_register_branch()
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/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-qoriq.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
31 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
37 struct clk *clk; member
42 struct clockgen_pll_div div[MAX_PLL_DIV]; member
51 int div; /* PLL_DIVn */ member
80 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
89 struct clk *sysclk, *coreclk;
91 struct clk *cmux[NUM_CMUX];
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/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dclock.c5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clk.h>
18 * This structure is to store the src bit, div bit and prediv bit
19 * positions of the peripheral clocks of the src and div registers
33 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
34 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
35 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
36 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
37 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
38 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clk.h>
28 struct s5pc100_clock *clk = in s5pc100_get_pll_clk() local
35 r = readl(&clk->apll_con); in s5pc100_get_pll_clk()
38 r = readl(&clk->mpll_con); in s5pc100_get_pll_clk()
41 r = readl(&clk->epll_con); in s5pc100_get_pll_clk()
44 r = readl(&clk->hpll_con); in s5pc100_get_pll_clk()
79 struct s5pc110_clock *clk = in s5pc110_get_pll_clk() local
86 r = readl(&clk->apll_con); in s5pc110_get_pll_clk()
89 r = readl(&clk->mpll_con); in s5pc110_get_pll_clk()
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/OK3568_Linux_fs/kernel/drivers/clk/mxs/
H A Dclk-div.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
9 #include "clk.h"
12 * struct clk_div - mxs integer divider clock
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dmeson-mx-sdhc-clkc.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
13 #include "meson-mx-sdhc.h"
19 struct clk_divider div; member
34 { .div = 6, .val = 5, },
35 { .div = 8, .val = 7, },
36 { .div = 9, .val = 8, },
37 { .div = 10, .val = 9, },
38 { .div = 12, .val = 11, },
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c4 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/kona-common/clk.h>
19 #include "clk-core.h"
30 struct clk *c; in clk_get_and_enable()
41 return -EINVAL; in clk_get_and_enable()
74 return -ETIMEDOUT; in wait_bit()
78 static int peri_clk_enable(struct clk *c, int enable) in peri_clk_enable()
83 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
84 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
85 void *base = (void *)c->ccu_clk_mgr_base; in peri_clk_enable()
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c4 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/kona-common/clk.h>
19 #include "clk-core.h"
30 struct clk *c; in clk_get_and_enable()
41 return -EINVAL; in clk_get_and_enable()
74 return -ETIMEDOUT; in wait_bit()
78 static int peri_clk_enable(struct clk *c, int enable) in peri_clk_enable()
83 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
84 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
85 void *base = (void *)c->ccu_clk_mgr_base; in peri_clk_enable()
[all …]

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