Searched +full:cdns +full:- +full:pcie +full:- +full:host (Results 1 – 15 of 15) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only3 ---4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Cadence PCIe host controller10 - Tom Joseph <tjoseph@cadence.com>13 - $ref: /schemas/pci/pci-bus.yaml#14 - $ref: "cdns-pcie-host.yaml#"18 const: cdns,cdns-pcie-host23 reg-names:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"7 title: Cadence PCIe Host10 - Tom Joseph <tjoseph@cadence.com>13 - $ref: "/schemas/pci/pci-bus.yaml#"14 - $ref: "cdns-pcie.yaml#"17 cdns,max-outbound-regions:25 cdns,no-bar-match-nbits:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/4 ---5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"8 title: TI J721E PCI Host (PCIe Wrapper)11 - Kishon Vijay Abraham I <kishon@ti.com>14 - $ref: "cdns-pcie-host.yaml#"19 - ti,j721e-pcie-host24 reg-names:[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Cadence PCIe platform driver.14 #include "pcie-cadence.h"19 * struct cdns_plat_pcie - private data for this PCIe platform driver20 * @pcie: Cadence PCIe controller21 * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,25 struct cdns_pcie *pcie; member35 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument49 struct device *dev = &pdev->dev; in cdns_plat_pcie_probe()59 return -EINVAL; in cdns_plat_pcie_probe()[all …]
1 // SPDX-License-Identifier: GPL-2.03 // Cadence PCIe endpoint controller driver.4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>9 #include <linux/pci-epc.h>13 #include "pcie-cadence.h"23 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local25 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()26 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()27 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()28 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, in cdns_pcie_ep_write_header()[all …]
1 // SPDX-License-Identifier: GPL-2.03 // Cadence PCIe host controller driver.4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>13 #include "pcie-cadence.h"31 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local32 unsigned int busn = bus->number; in cdns_pci_map_bus()44 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()47 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()49 /* Clear AXI link-down status */ in cdns_pci_map_bus()50 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/6 /dts-v1/;8 #include "k3-j721e-som-p0.dtsi"9 #include <dt-bindings/gpio/gpio.h>10 #include <dt-bindings/input/input.h>11 #include <dt-bindings/net/ti-dp83867.h>15 stdout-path = "serial2:115200n8";19 gpio_keys: gpio-keys {20 compatible = "gpio-keys";[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy.h>8 #include <dt-bindings/mux/mux.h>9 #include <dt-bindings/mux/ti-serdes.h>12 cmn_refclk: clock-cmnrefclk {13 #clock-cells = <0>;14 compatible = "fixed-clock";15 clock-frequency = <0>;18 cmn_refclk1: clock-cmnrefclk1 {[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/gpio/uniphier-gpio.h>10 #include <dt-bindings/thermal/thermal.h>13 compatible = "socionext,uniphier-pxs3";14 #address-cells = <2>;15 #size-cells = <2>;16 interrupt-parent = <&gic>;19 #address-cells = <2>;20 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/gpio/uniphier-gpio.h>10 #include <dt-bindings/thermal/thermal.h>13 compatible = "socionext,uniphier-ld20";14 #address-cells = <2>;15 #size-cells = <2>;16 interrupt-parent = <&gic>;19 #address-cells = <2>;[all …]
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
5 force -- enable ACPI if default was off6 on -- enable ACPI but allow fallback to DT [arm64]7 off -- disable ACPI if default was on8 noirq -- do not use ACPI for IRQ routing9 strict -- Be less tolerant of platforms that are not11 rsdt -- prefer RSDT over (default) XSDT12 copy_dsdt -- copy DSDT to memory26 If set to vendor, prefer vendor-specific driver58 Documentation/firmware-guide/acpi/debug.rst for more information about121 Disable auto-serialization of AML methods[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */5 * Copyright (C) 2018-2019 Cadence.6 * Copyright (C) 2017-2018 NXP17 * USBSS-DEV register interface.22 * struct cdns3_usb_regs - device controller registers.52 * @buf_addr: Address for On-chip Buffer operations.53 * @buf_data: Data for On-chip Buffer operations.54 * @buf_ctrl: On-chip Buffer Access Control.122 /* USB_CONF - bitmasks */131 /* Little Endian access - default */[all …]
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