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/OK3568_Linux_fs/kernel/include/linux/
H A Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 # define aligned_byte_mask(n) ((1UL << 8*(n))-1)
11 # define aligned_byte_mask(n) (~0xffUL << (BITS_PER_LONG - 8 - 8*(n)))
31 #define for_each_set_bit(bit, addr, size) \ argument
32 for ((bit) = find_first_bit((addr), (size)); \
33 (bit) < (size); \
34 (bit) = find_next_bit((addr), (size), (bit) + 1))
36 /* same as for_each_set_bit() but use bit as value to start with */
37 #define for_each_set_bit_from(bit, addr, size) \ argument
38 for ((bit) = find_next_bit((addr), (size), (bit)); \
[all …]
H A Dmath64.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
16 * @dividend: unsigned 64bit dividend
17 * @divisor: unsigned 32bit divisor
18 * @remainder: pointer to unsigned 32bit remainder
22 * This is commonly provided by 32bit archs to provide an optimized 64bit
32 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
33 * @dividend: signed 64bit dividend
34 * @divisor: signed 32bit divisor
35 * @remainder: pointer to signed 32bit remainder
[all …]
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
31 #clock-cells = <0>;
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H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
26 ti,max-div = <3>;
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H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
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H A Domap34xx-omap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
17 #clock-cells = <0>;
18 compatible = "ti,omap3-interface-clock";
20 ti,bit-shift = <3>;
25 #clock-cells = <0>;
26 compatible = "ti,omap3-interface-clock";
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H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
32 #clock-cells = <0>;
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H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <59000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <12000000>;
21 #clock-cells = <0>;
22 compatible = "ti,gate-clock";
24 ti,bit-shift = <8>;
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H A Domap3430es1-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
20 ti,max-div = <7>;
22 ti,index-starts-at-one;
26 #clock-cells = <0>;
27 compatible = "fixed-factor-clock";
[all …]
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
15 #clock-cells = <0>;
16 compatible = "ti,dra7-atl-clock";
21 #clock-cells = <0>;
22 compatible = "ti,dra7-atl-clock";
27 #clock-cells = <0>;
28 compatible = "ti,dra7-atl-clock";
33 #clock-cells = <0>;
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Domap3xxx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
28 ti,bit-shift = <6>;
29 ti,max-div = <3>;
31 ti,index-starts-at-one;
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H A Ddra7xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
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H A Domap34xx-omap36xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <1>;
20 #clock-cells = <0>;
21 compatible = "ti,omap3-interface-clock";
23 ti,bit-shift = <3>;
28 #clock-cells = <0>;
29 compatible = "ti,omap3-interface-clock";
32 ti,bit-shift = <2>;
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H A Dam43xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
15 ti,bit-shift = <31>;
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
23 ti,bit-shift = <29>;
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
31 ti,bit-shift = <22>;
36 #clock-cells = <0>;
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/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra30-mc.h>
45 .bit = 1,
49 .shift = 0,
59 .bit = 2,
63 .shift = 0,
73 .bit = 3,
77 .shift = 16,
87 .bit = 4,
91 .shift = 16,
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H A Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra210-mc.h>
21 .bit = 1,
25 .shift = 0,
35 .bit = 2,
39 .shift = 0,
49 .bit = 3,
53 .shift = 16,
63 .bit = 4,
67 .shift = 16,
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H A Dtegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra114-mc.h>
24 .bit = 1,
28 .shift = 0,
38 .bit = 2,
42 .shift = 0,
52 .bit = 3,
56 .shift = 16,
66 .bit = 4,
70 .shift = 16,
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H A Dtegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra124-mc.h>
24 .bit = 1,
28 .shift = 0,
38 .bit = 2,
42 .shift = 0,
52 .bit = 3,
56 .shift = 16,
66 .bit = 4,
70 .shift = 16,
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/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_qmath.c1 // SPDX-License-Identifier: ISC
9 * Description: This function make 16 bit unsigned multiplication.
10 * To fit the output into 16 bits the 32 bit multiplication result is right
19 * Description: This function make 16 bit multiplication and return the result
22 * is done to remove the extra sign bit formed due to the multiplication.
23 * When both the 16bit inputs are 0x8000 then the output is saturated to
38 * Description: This function add two 32 bit numbers and return the 32bit
55 * Description: This function add two 16 bit numbers and return the 16bit
74 * Description: This function make 16 bit subtraction and return the 16bit
81 s32 temp = (s32) op1 - (s32) op2; in qm_sub16()
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/OK3568_Linux_fs/u-boot/include/linux/
H A Dmath64.h14 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
16 * This is commonly provided by 32bit archs to provide an optimized 64bit
26 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
35 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
44 * div64_u64 - unsigned 64bit divide with 64bit divisor
52 * div64_s64 - signed 64bit divide with 64bit divisor
91 * div_u64 - unsigned 64bit divide with 32bit divisor
93 * This is the most common 64bit divide and should be used if possible,
94 * as many 32bit archs can optimize this variant better than a full 64bit
106 * div_s64 - signed 64bit divide with 32bit divisor
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/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Dtmio.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define sd_config_write8(base, shift, reg, val) \ argument
29 tmio_iowrite8((val), (base) + ((reg) << (shift)))
30 #define sd_config_write16(base, shift, reg, val) \ argument
31 tmio_iowrite16((val), (base) + ((reg) << (shift)))
32 #define sd_config_write32(base, shift, reg, val) \ argument
34 tmio_iowrite16((val), (base) + ((reg) << (shift))); \
35 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
40 * Some controllers can support a 2-byte block size when the bus width
41 * is configured in 4-bit mode.
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/OK3568_Linux_fs/kernel/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ti/
H A Dgate.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 quite much similar to the basic gate-clock [2], however,
9 will be controlled instead and the corresponding hw-ops for
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
17 - compatible : shall be one of:
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
22 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
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/OK3568_Linux_fs/kernel/drivers/pinctrl/bcm/
H A Dpinctrl-iproc-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2017 Broadcom
9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
65 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
123 * Mapping from PINCONF pins to GPIO pins is 1-to-1
131 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
143 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in iproc_set_bit() local
146 val = readl(chip->base + offset); in iproc_set_bit()
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