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6 * SPDX-License-Identifier: GPL-2.0+84 /* Disable windows, set size/base/remap to 0 */ in mvebu_lcd_conf_mbus_registers()92 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()93 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()94 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in mvebu_lcd_conf_mbus_registers()95 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()98 writel(cs->base & 0xffff0000, MVEBU_LCD_WIN_BASE(i)); in mvebu_lcd_conf_mbus_registers()106 int x = lcd_info->x_res; in mvebu_lcd_register_init()107 int y = lcd_info->y_res; in mvebu_lcd_register_init()114 * Set LVDS Pads Control Register in mvebu_lcd_register_init()[all …]
4 Copyright 2008-2022 NXP12 The driver code supports Linux kernel from 2.6.32 to 6.0.0.16 a) Copy firmware image to /lib/firmware/nxp/, copy wifi_mod_para.conf to /lib/firmware/nxp/.19 The bit settings of drv_mode are,20 Bit 0 : STA21 Bit 1 : uAP22 Bit 2 : WIFIDIRECT31 uap_oper_ctrl: uAP operation control when in-STA disconnect with ext-AP33 For example, to install multi-chip driver,36 …wifi_mod_para.conf is used to support multi-chips which has different load module parameters. It c…[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */4 * Copyright (c) 2012 Guenter Roeck <linux@roeck-us.net>13 * For all bit masks:14 * bit 0: local temperature15 * bit 1..7: remote temperatures18 bool smbus_timeout_disable; /* set to disable SMBus timeouts */19 bool extended_range_enable; /* set to enable extended temp range */20 bool beta_compensation; /* set to enable beta compensation */21 u8 alert_mask; /* set bit to 1 to disable alert */22 u8 over_temperature_mask; /* set bit to 1 to disable */[all …]
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */17 #define IDE_DRIVE_TASK_INVALID -1137 * 0x01->0x02 Reserved141 * 0x04->0x07 Reserved146 * 0x09->0x0F Reserved151 * 0x10->0x1F Reserved153 #define WIN_READ 0x20 /* 28-Bit */154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */155 #define WIN_READ_LONG 0x22 /* 28-Bit */156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */[all …]
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */16 #define IDE_DRIVE_TASK_INVALID -1128 * 0x01->0x02 Reserved132 * 0x04->0x07 Reserved137 * 0x09->0x0F Reserved142 * 0x10->0x1F Reserved144 #define WIN_READ 0x20 /* 28-Bit */145 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */146 #define WIN_READ_LONG 0x22 /* 28-Bit */147 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */[all …]
... :AENC: input buffer not Audio type. Fail to fill audio frame Fail to send frame to encoder name ...
6 register contains several bit fields with one bit or several bits7 to configure for some global common configuration, such as domain12 to choose one function (like: UART0) for which system, since we16 of them, so we can not make every Spreadtrum-special configuration18 global configuration in future. Then we add one "sprd,control" to19 set these various global control configuration, and we need use22 Moreover we recognise every fields comprising one bit or several24 record every pin's bit offset, bit width and register offset to29 to configure the pin sleep mode, function select and sleep related35 - input-enable[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 #clock-cells = <0>;10 compatible = "ti,omap3-dpll-per-j-type-clock";16 #clock-cells = <0>;17 compatible = "ti,hsdiv-gate-clock";19 ti,bit-shift = <0x1e>;21 ti,set-rate-parent;22 ti,set-bit-to-disable;26 #clock-cells = <0>;27 compatible = "ti,hsdiv-gate-clock";[all …]
12 #clock-cells = <0>;13 compatible = "ti,omap3-dpll-per-j-type-clock";19 #clock-cells = <0>;20 compatible = "ti,hsdiv-gate-clock";22 ti,bit-shift = <0x1e>;24 ti,set-rate-parent;25 ti,set-bit-to-disable;29 #clock-cells = <0>;30 compatible = "ti,hsdiv-gate-clock";32 ti,bit-shift = <0x1b>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (C) 2007-2009 ST-Ericsson AB35 /* Reset OS Timer 32bit (-/W) */38 /* Enable OS Timer 32bit (-/W) */41 /* Disable OS Timer 32bit (-/W) */44 /* OS Timer Mode Register 32bit (-/W) */48 /* OS Timer Status Register 32bit (R/-) */59 /* OS Timer Current Count Register 32bit (R/-) */61 /* OS Timer Terminal Count Register 32bit (R/W) */63 /* OS Timer Interrupt Enable Register 32bit (-/W) */[all …]
5 force -- enable ACPI if default was off6 on -- enable ACPI but allow fallback to DT [arm64]7 off -- disable ACPI if default was on8 noirq -- do not use ACPI for IRQ routing9 strict -- Be less tolerant of platforms that are not11 rsdt -- prefer RSDT over (default) XSDT12 copy_dsdt -- copy DSDT to memory26 If set to vendor, prefer vendor-specific driver29 If set to video, use the ACPI video.ko driver.30 If set to native, use the device's native backlight mode.[all …]
4 - compatible:16 - reg: I2C address20 - smbus-timeout-disable21 Set to disable SMBus timeout. If not specified, SMBus timeout will be23 - extended-range-enable24 Only valid for MAX6581. Set to enable extended temperature range.26 - beta-compensation-enable27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on30 - alert-mask31 Alert bit mask. Alert disabled for bits set.[all …]
1 // SPDX-License-Identifier: GPL-2.03 * arch/sh/boards/mach-x3proto/ilsel.c5 * Helper routines for SH-X3 proto board ILSEL.7 * Copyright (C) 2007 - 2010 Paul Mundt21 * ILSEL0 - 0xb8100004 [ Levels 1 - 4 ]22 * ILSEL1 - 0xb8100006 [ Levels 5 - 8 ]23 * ILSEL2 - 0xb8100008 [ Levels 9 - 12 ]24 * ILSEL3 - 0xb810000a [ Levels 13 - 15 ]26 * With each level being relative to an ilsel_source_t.34 * Supported levels are 1 - 15 spread across ILSEL0 - ILSEL4, mapping[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */3 * Copyright (C) 2017-2020 Jacopo Mondi4 * Copyright (C) 2017-2020 Kieran Bingham5 * Copyright (C) 2017-2020 Laurent Pinchart6 * Copyright (C) 2017-2020 Niklas Söderlund23 #define MAX9271_R02_RES BIT(4)27 #define MAX9271_SEREN BIT(7)28 #define MAX9271_CLINKEN BIT(6)29 #define MAX9271_PRBSEN BIT(5)30 #define MAX9271_SLEEP BIT(4)[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */4 Copyright © 1997-1998 by PowerLogix R & D, Inc.9 - First public release, contributed by PowerLogix.12 - Terry: Made sure code disabled interrupts before running. (Previously14 - Terry: Updated for tentative G4 support. 4MB of memory is now flushed16 - Terry: Updated for workaround to HID0[DPM] processor bug20 - Terry: Added isync to correct for an errata.23 - DanM: Finally added the 7450 patch I've had for the past25 to assume the user of this functions knows what they29 Please e-mail updates to this file to me, thanks![all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later9 * any of this software. This material is provided "AS-IS" in12 * (C) Copyright 2003-2006 Sven Anders <anders@anduras.de>15 * 2003 - Created version 1.0 for Linux 2.4.x.16 * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE30 * for yet another little while to reset the system.32 * notifications cease to occur, and the hardware watchdog will38 * For an example userspace keep-alive daemon, see:82 static DEFINE_SPINLOCK(io_lock);/* to guard the watchdog from io races */86 /* -- Low level function ----------------------------------------*/[all …]
2 * Copyright (C) 2007-2009 coresystems GmbH7 * SPDX-License-Identifier: GPL-2.0+13 * The programming interface is common to most Intel chipsets. But the PRTx14 * registers may be mapped to different blocks. Some chipsets map them to LPC16 * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy19 * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines20 * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be29 /* Disable method */53 /* Set the bit from PRTA */59 /* Set Resource Setting for this IRQ link */[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */8 * Check document WM-20151103-v02-JackieLau-RTL8822B_Power_Architecture.vsd10 * 0: POFF--Power Off11 * 1: PDN--Power Down12 * 2: CARDEMU--Card Emulation13 * 3: ACT--Active Mode14 * 4: LPS--Low Power State15 * 5: SUS--Suspend44 …LMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, …45 …HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*0x67[0] = 0 to…[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (C) 2014-2017 Broadcom9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic14 * individually muxed to GPIO function, if individual pad29 #include <linux/pinctrl/pinconf-generic.h>31 #include "../pinctrl-utils.h"65 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)84 * @dev: pointer to device88 * @lock: lock to protect access to I/O registers90 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs[all …]
1 // SPDX-License-Identifier: GPL-2.0-only17 #define PRODUCER_CRCI_X_SEL BIT(0)18 #define PRODUCER_CRCI_Y_SEL BIT(1)21 #define CONSUMER_CRCI_X_SEL BIT(2)22 #define CONSUMER_CRCI_Y_SEL BIT(3)23 #define PRODUCER_TRANS_END_EN BIT(4)24 #define BYPASS BIT(16)25 #define DIRECT_MODE BIT(17)26 #define INFINITE_CONS_TRANS BIT(18)51 void __iomem *base = host->base + DML_OFFSET; in qcom_dma_start()[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */9 * 0: POFF--Power Off10 * 1: PDN--Power Down11 * 2: CARDEMU--Card Emulation12 * 3: ACT--Active Mode13 * 4: LPS--Low Power State14 * 5: SUS--Suspend43 …LMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, …44 …HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*0x67[0] = 0 to…46 …PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /*0x00[5] = 1b'0 releas…[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S310 * https://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf12 * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).24 #define DRV_NAME "rtc-ab-b5ze-s3"28 #define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */29 #define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */30 #define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */31 #define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */32 #define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */30 /* Yukon-2 */32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */[all …]
8 :Copyright: |copy| 2002-2011 Sentelic Corporation.10 :Last update: Dec-07-201118 1. Set sample rate to 200;19 2. Set sample rate to 200;20 3. Set sample rate to 80;27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 028 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|30 |---------------| |---------------| |---------------| |---------------|34 Bit5 => Y sign bit35 Bit4 => X sign bit[all …]