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/OK3568_Linux_fs/kernel/drivers/net/hamradio/
H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 #define AUTO_ENAB 0x20 /* Auto Enables */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
145 /* Write Register 12 (lower byte of baud rate generator time constant) */
147 /* Write Register 13 (upper byte of baud rate generator time constant) */
150 #define BRENABL 1 /* Baud rate generator enable */
151 #define BRSRC 2 /* Baud rate generator source */
153 #define AUTOECHO 8 /* Auto Echo */
[all …]
/OK3568_Linux_fs/kernel/drivers/tty/serial/
H A Dmxs-auart.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
34 #include <linux/dma-mapping.h>
140 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
142 * input is idle, then the watchdog counter will decrement each bit-time. Note
143 * 7-bit-time is added to the programmed value, so a value of zero will set
144 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
148 * value is 0x3 (31 bit-time).
151 /* TIMEOUT = (100*7+1)*(1/BAUD) */
[all …]
H A Dsuncore.c1 // SPDX-License-Identifier: GPL-2.0
32 drv->minor = sunserial_current_minor; in sunserial_register_minors()
33 drv->nr += count; in sunserial_register_minors()
35 if (drv->nr == count) in sunserial_register_minors()
39 drv->tty_driver->name_base = drv->minor - 64; in sunserial_register_minors()
47 drv->nr -= count; in sunserial_unregister_minors()
48 sunserial_current_minor -= count; in sunserial_unregister_minors()
50 if (drv->nr == 0) in sunserial_unregister_minors()
61 drv->cons = con; in sunserial_console_match()
78 con->index = line; in sunserial_console_match()
[all …]
H A Dmax310x.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
49 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
63 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
64 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
65 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
102 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
115 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
116 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
119 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
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H A Dmilbeaut_usio.c1 // SPDX-License-Identifier: GPL-2.0
15 #define USIO_NAME "mlb-usio-uart"
67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
75 struct circ_buf *xmit = &port->state->xmit; in mlb_usio_tx_chars()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
[all …]
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
94 #define AUTO_ENAB 0x20 /* Auto Enables */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
181 /* Write Register 12 (lower byte of baud rate generator time constant) */
183 /* Write Register 13 (upper byte of baud rate generator time constant) */
186 #define BRENAB 1 /* Baud rate generator enable */
187 #define BRSRC 2 /* Baud rate generator source */
[all …]
H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
113 #define AUTO_ENAB 0x20 /* Auto Enables */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
200 /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
202 /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
205 #define BRENABL 1 /* Baud rate generator enable */
[all …]
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
86 #define AUTO_ENAB 0x20 /* Auto Enables */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
183 /* Write Register 12 (lower byte of baud rate generator time constant) */
185 /* Write Register 13 (upper byte of baud rate generator time constant) */
188 #define BRENAB 1 /* Baud rate generator enable */
189 #define BRSRC 2 /* Baud rate generator source */
[all …]
H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
74 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
76 return uap->mate; in pmz_get_port_A()
88 writeb(reg, port->control_reg); in read_zsreg()
89 return readb(port->control_reg); in read_zsreg()
95 writeb(reg, port->control_reg); in write_zsreg()
96 writeb(value, port->control_reg); in write_zsreg()
101 return readb(port->data_reg); in read_zsdata()
106 writeb(data, port->data_reg); in write_zsdata()
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H A Dfsl_lpuart.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
10 #include <linux/dma-mapping.h>
23 /* All registers are 8-bit width */
112 /* 32-bit register definition */
225 #define DRIVER_NAME "fsl-lpuart"
302 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
303 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
304 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
305 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
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H A Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
46 * - only on 75x/76x
49 * - only on 75x/76x
52 * - only on 75x/76x
55 * - only on 75x/76x
83 /* IER register bits - write only if (EFR[4] == 1) */
96 /* FCR register bits - write only if (EFR[4] == 1) */
106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108 * - only on 75x/76x
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/serial/
H A Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
19 where N is the port number (non-negative decimal integer) as printed on the
26 cts-gpios:
32 dcd-gpios:
38 dsr-gpios:
44 dtr-gpios:
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/OK3568_Linux_fs/u-boot/include/
H A Dfsl_qe.h2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
22 #define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
75 /* QE CECR Sub Block Code - sub block code of QE command.
109 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
135 QE_BRG1, /* Baud Rate Generator 1 */
136 QE_BRG2, /* Baud Rate Generator 2 */
137 QE_BRG3, /* Baud Rate Generator 3 */
138 QE_BRG4, /* Baud Rate Generator 4 */
139 QE_BRG5, /* Baud Rate Generator 5 */
[all …]
H A Dns16550.h15 * added support for port on 64-bit bus
31 #define CONFIG_SYS_NS16550_REG_SIZE (-1)
40 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
45 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
49 * struct ns16550_platdata - information about a NS16550 port
121 /* Ingenic JZ47xx specific UART-enable bit. */
137 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
211 * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
218 * @baudrate: Required baud rate
219 * @return baud rate divisor that should be used
[all …]
/OK3568_Linux_fs/kernel/drivers/tty/serial/jsm/
H A Djsm_neo.c1 // SPDX-License-Identifier: GPL-2.0+
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
43 /* Turn on auto CTS flow control */ in neo_set_cts_flow_control()
47 /* Turn off auto Xon flow control */ in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wan/
H A Dz85230.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
82 #define AUTO_ENAB 0x20 /* Auto Enables */
112 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
121 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
123 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
166 /* Write Register 12 (lower byte of baud rate generator time constant) */
168 /* Write Register 13 (upper byte of baud rate generator time constant) */
171 #define BRENABL 1 /* Baud rate generator enable */
172 #define BRSRC 2 /* Baud rate generator source */
[all …]
/OK3568_Linux_fs/kernel/drivers/tty/serial/8250/
H A D8250_fintek.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
104 outb(reg, pdata->base_port + ADDR_PORT); in sio_read_reg()
105 return inb(pdata->base_port + DATA_PORT); in sio_read_reg()
110 outb(reg, pdata->base_port + ADDR_PORT); in sio_write_reg()
111 outb(data, pdata->base_port + DATA_PORT); in sio_write_reg()
126 return -EBUSY; in fintek_8250_enter_key()
148 return -ENODEV; in fintek_8250_check_id()
151 return -ENODEV; in fintek_8250_check_id()
165 return -ENODEV; in fintek_8250_check_id()
[all …]
H A D8250_port.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
259 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
260 * workaround of errata A-008006 which states that tx_loadsz should
272 .name = "Palmchip BK-3103",
344 -1, /* UART_SCR (unmapped) */
353 -1, /* UART_LSR (unmapped) */
354 -1, /* UART_MSR (unmapped) */
355 -1, /* UART_SCR (unmapped) */
365 return __raw_readl(p->membase + (offset << p->regshift)); in au_serial_in()
[all …]
H A D8250_exar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
53 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
59 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
60 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
81 * ---- ---- --------
85 * 3 - <reserved>
89 * 7 - <reserved>
92 * 10 - Red LED
93 * 11..15 - <unused>
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/serial/
H A Dcp210x.c1 // SPDX-License-Identifier: GPL-2.0
9 * control thanks to Munir Nassar nassarmu@real-time.com
59 { USB_DEVICE(0x045B, 0x0053) }, /* Renesas RX610 RX-Stick */
60 { USB_DEVICE(0x0471, 0x066A) }, /* AKTAKOM ACE-1001 cable */
61 { USB_DEVICE(0x0489, 0xE000) }, /* Pirelli Broadband S.p.A, DP-L10 SIP/GSM Mobile */
62 { USB_DEVICE(0x0489, 0xE003) }, /* Pirelli Broadband S.p.A, DP-L10 SIP/GSM Mobile */
65 { USB_DEVICE(0x08e6, 0x5501) }, /* Gemalto Prox-PU/CU contactless smartcard reader */
70 { USB_DEVICE(0x0BED, 0x1100) }, /* MEI (TM) Cashflow-SC Bill/Voucher Acceptor */
75 { USB_DEVICE(0x0FDE, 0xCA05) }, /* OWL Wireless Electricity Monitor CM-160 */
77 { USB_DEVICE(0x10A6, 0xAA26) }, /* Knock-off DCU-11 cable */
[all …]
/OK3568_Linux_fs/kernel/include/soc/fsl/qe/
H A Dqe.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 QE_BRG1, /* Baud Rate Generator 1 */
40 QE_BRG2, /* Baud Rate Generator 2 */
41 QE_BRG3, /* Baud Rate Generator 3 */
42 QE_BRG4, /* Baud Rate Generator 4 */
43 QE_BRG5, /* Baud Rate Generator 5 */
44 QE_BRG6, /* Baud Rate Generator 6 */
45 QE_BRG7, /* Baud Rate Generator 7 */
46 QE_BRG8, /* Baud Rate Generator 8 */
47 QE_BRG9, /* Baud Rate Generator 9 */
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/share/doc/gdb/
H A DRemote-Configuration.html1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dt…
3 <!-- Copyright (C) 1988-2021 Free Software Foundation, Inc.
9 Free Documentation", with the Front-Cover Texts being "A GNU Manual,"
10 and with the Back-Cover Texts as in (a) below.
12 (a) The FSF's Back-Cover Text is: "You are free to copy and modify
14 developing GNU and promoting software freedom." -->
15 <!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ -->
21 <meta name="resource-type" content="document">
24 <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
26 <link href="Concept-Index.html#Concept-Index" rel="index" title="Concept Index">
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/share/doc/gdb/
H A DRemote-Configuration.html1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dt…
3 <!-- Copyright (C) 1988-2021 Free Software Foundation, Inc.
9 Free Documentation", with the Front-Cover Texts being "A GNU Manual,"
10 and with the Back-Cover Texts as in (a) below.
12 (a) The FSF's Back-Cover Text is: "You are free to copy and modify
14 developing GNU and promoting software freedom." -->
15 <!-- Created by GNU Texinfo 5.1, http://www.gnu.org/software/texinfo/ -->
21 <meta name="resource-type" content="document">
24 <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
26 <link href="Concept-Index.html#Concept-Index" rel="index" title="Concept Index">
[all …]
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dbcm3510_priv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2001-5, B2C2 inc.
267 /* auto reacquire */
301 u8 PE :1; /* baud clock pin */
303 u8 BE :1; /* baud clock pin */
364 u8 ARI :1; /* auto reacquire */
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
39 #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
40 #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
59 #define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
83 #define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */

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