Searched +full:assign +full:- +full:clock +full:- +full:rates (Results 1 – 25 of 56) sorted by relevance
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1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Rockchip Clock Out Control Module Binding10 - Sugar Zhang <sugar.zhang@rock-chips.com>13 This add support switch for clk-bidirection which located21 (which means Input default for clk-bidrection) in the pre-stage,22 such boot-loader or init by HW default. And then set a safety freq23 before enable clk-out, such as "assign-clock-rates" or clk_set_rate[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later31 /* standard rates */82 /* double rates */151 if (pcm->spdif) in get_slot_reg()153 if (pcm->stream == SNDRV_PCM_STREAM_PLAYBACK) in get_slot_reg()154 return rate_reg_tables[dbl][pcm->r[dbl].rate_table[cidx]][slot - 3]; in get_slot_reg()156 return rate_cregs[slot - 3]; in get_slot_reg()164 if (! (ac97->ext_id & AC97_EI_SPDIF)) in set_spdif_rate()165 return -ENODEV; in set_spdif_rate()168 if (ac97->flags & AC97_CS_SPDIF) { in set_spdif_rate()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * i2sbus driver -- pcm routines23 *pi = &i2sdev->in; in get_pcm_info()25 *other = &i2sdev->out; in get_pcm_info()28 *pi = &i2sdev->out; in get_pcm_info()30 *other = &i2sdev->in; in get_pcm_info()38 return -1; in clock_and_divisors()41 return -1; in clock_and_divisors()61 return -1; in clock_and_divisors()65 do { if (rates & SNDRV_PCM_RATE_ ##rate) { \[all …]
8 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH9 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH10 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-649730 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH31 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH32 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation65 #include "iwl-io.h"66 #include "iwl-prph.h"67 #include "fw-api.h"[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */24 #define ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */40 /* ESP config reg 1, read-write, found on all ESP chips */48 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */52 #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */55 #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */58 #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */63 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */64 #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */65 #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */[all …]
1 // SPDX-License-Identifier: GPL-2.0-only20 #include "max98373-sdw.h"250 regcache_cache_only(max98373->regmap, true); in max98373_suspend()251 regcache_mark_dirty(max98373->regmap); in max98373_suspend()261 if (!max98373->first_hw_init) in max98373_resume()264 if (!slave->unattach_request) in max98373_resume()267 time = wait_for_completion_timeout(&slave->initialization_complete, in max98373_resume()271 return -ETIMEDOUT; in max98373_resume()275 slave->unattach_request = 0; in max98373_resume()276 regcache_cache_only(max98373->regmap, false); in max98373_resume()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later21 /* for art-tsc conversion */38 /* assign a stream for the PCM */60 return &apcm->info->stream[substream->stream]; in to_hda_pcm_stream()70 if (!hinfo->ops.get_delay) in azx_adjust_codec_delay()73 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); in azx_adjust_codec_delay()75 substream->runtime->rate); in azx_adjust_codec_delay()77 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in azx_adjust_codec_delay()80 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; in azx_adjust_codec_delay()91 struct azx *chip = apcm->chip; in azx_pcm_close()[all …]
1 // SPDX-License-Identifier: GPL-2.03 * camss-csid.c5 * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.8 * Copyright (C) 2015-2018 Linaro Ltd.19 #include <media/media-entity.h>20 #include <media/v4l2-device.h>21 #include <media/v4l2-event.h>22 #include <media/v4l2-subdev.h>24 #include "camss-csid.h"[all …]
3 文件标识：RK-PC-YF-4047 日期：2023-06-2833 网址： [www.rock-chips.com](http://www.rock-chips.com)35 客户服务电话： +86-4007-700-59037 客户服务传真： +86-591-8395183339 客户服务邮箱： [fae@rock-chips.com](mailto:fae@rock-chips.com)41 ---47 - 技术支持工程师48 - 软件开发工程师53 | ---------- | -------- | -------- | ------------------------------- |[all …]
3 File No.：RK-PC-YF-4047 Release Date: 2023-06-289 Security Level: □Top-Secret □Secret □Internal ■Public13 …ITY, COMPLETENESS,MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY R…27 Website: [www.rock-chips.com](http://www.rock-chips.com)29 Customer service Tel: +86-4007-700-59031 Customer service Fax: +86-591-8395183333 Customer service e-Mail: [fae@rock-chips.com](mailto:fae@rock-chips.com)35 ---41 - Technical support engineers[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later28 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */33 static int ac97_codec = -1;40 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");46 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");144 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))170 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */240 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */286 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),302 void __iomem *addr = chip->remap_addr + reg; in snd_atiixp_update_bits()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only5 * Copyright (C) 2004-2007, David Dillow7 * Inspired by the Trident 4D-WaveDX/NX driver.29 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */53 * we use the hardware's built-in Mid-Loop Interrupt and End-Loop Interrupt63 * channel to clock out virtual periods, and adjust the virtual period length142 * documented range of 8-0xfff8 samples. Given that they are 0-based,143 * that places our period/buffer range at 9-0xfff9 samples. That makes the159 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_CONTINUOUS,180 .rates = SNDRV_PCM_RATE_48000,[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later8 * Tjeerd.Mulder <Tjeerd.Mulder@fujitsu-siemens.com>16 * - use the DSX channels for the first pcm playback.19 * multi-channel playback is assigned to the second device21 * - support the secondary capture (on VIA8233/C,8235)22 * - SPDIF support26 * the card config of alsa-lib will assign the correct28 * - clean up the code, separate low-level initialization32 * - Optimize position calculation for the 823x chips. 65 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later9 * Rewritted from card-es1938.c source.27 * encoding. The codecs are almost always AC-97 compliant codecs, 36 * mixers in the codecs. There are 64 APUs. We assign 6 to each88 #include <linux/dma-mapping.h>102 #include <media/drv-intf/tea575x.h>119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */122 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };123 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };124 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };[all …]
1 // SPDX-License-Identifier: GPL-2.0-only5 * Copyright (C) 2005-2009 Atmel Corporation57 #define get_chip(card) ((struct atmel_ac97c *)(card)->private_data)60 __raw_writel((val), (chip)->regs + AC97C_##reg)62 __raw_readl((chip)->regs + AC97C_##reg)74 .rates = (SNDRV_PCM_RATE_CONTINUOUS),89 struct snd_pcm_runtime *runtime = substream->runtime; in atmel_ac97c_playback_open()92 chip->opened++; in atmel_ac97c_playback_open()93 runtime->hw = atmel_ac97c_hw; in atmel_ac97c_playback_open()94 if (chip->cur_rate) { in atmel_ac97c_playback_open()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */16 #include <sound/pcm-indirect.h>25 /* ------------------- DEFINES -------------------- */37 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */55 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */57 /* accessed. For non per-channel registers the */93 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */106 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */111 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */115 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst10 #include <linux/clk-provider.h>11 #include <linux/clk/clk-conf.h>115 if (!core->rpm_enabled) in clk_pm_runtime_get()118 ret = pm_runtime_get_sync(core->dev); in clk_pm_runtime_get()120 pm_runtime_put_noidle(core->dev); in clk_pm_runtime_get()128 if (!core->rpm_enabled) in clk_pm_runtime_put()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later10 - spdif nonaudio consumer mode does not work (at least with my11 Sony STR-DB830)18 * split the code to several files. each low-level routine25 * I also haven't done anything with the internal S/PDIF transmitter or the MPU-40140 #include <linux/dma-mapping.h>70 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */75 static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transcei…85 MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");112 /* check whether the clock mode is spdif-in */[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver28 #define DRIVER_NAME "aaci-pl041"39 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); in aaci_ac97_select_codec()44 v = readl(aaci->base + AACI_SLFR); in aaci_ac97_select_codec()46 readl(aaci->base + AACI_SL2RX); in aaci_ac97_select_codec()48 readl(aaci->base + AACI_SL1RX); in aaci_ac97_select_codec()50 if (maincr != readl(aaci->base + AACI_MAINCR)) { in aaci_ac97_select_codec()51 writel(maincr, aaci->base + AACI_MAINCR); in aaci_ac97_select_codec()52 readl(aaci->base + AACI_MAINCR); in aaci_ac97_select_codec()[all …]
1 // SPDX-License-Identifier: GPL-2.023 #include "imx-audmux.h"38 * struct codec_priv - CODEC private data39 * @mclk_freq: Clock rate of MCLK40 * @mclk_id: MCLK (or main clock) id for set_sysclk()41 * @fll_id: FLL (or secordary clock) id for set_sysclk()52 * struct cpu_priv - CPU private data53 * @sysclk_freq: SYSCLK rates for set_sysclk()68 * struct fsl_asoc_card_priv - Freescale Generic ASOC card private data79 * @asrc_rate: ASRC sample rate used by Back-Ends[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>9 * Based on sdhci-of-esdhc.c18 #include <linux/clk-provider.h>25 #include <linux/firmware/xlnx-zynqmp.h>28 #include "sdhci-cqhci.h"29 #include "sdhci-pltfm.h"48 /* Default settings for ZynqMP Clock Phases */56 * On some SoCs the syscon area has a feature where the upper 16-bits of57 * each 32-bit register act as a write mask for the lower 16-bits. This allows[all …]
11 Architecture) <http://www.alsa-project.org/>`__ driver. The document19 low-level driver implementation details. It only describes the standard29 -------61 --------------65 sub-directories contain different modules and are dependent upon the74 ``core/seq/oss`` directory (see `below <#core-seq-oss>`__).79 This directory and its sub-directories are for the ALSA sequencer. This81 like snd-seq-midi, snd-seq-virmidi, etc. They are compiled only when90 -----------------93 to be exported to user-space, or included by several files at different[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 // soc-topology.c -- ALSA SoC Topology29 #include <sound/soc-dapm.h>30 #include <sound/soc-topology.h>90 const u8 *end = tplg->pos + elem_size * count; in soc_tplg_check_elem_count()92 if (end > tplg->fw->data + tplg->fw->size) { in soc_tplg_check_elem_count()93 dev_err(tplg->dev, "ASoC: %s overflow end of data\n", in soc_tplg_check_elem_count()95 return -EINVAL; in soc_tplg_check_elem_count()101 dev_err(tplg->dev, in soc_tplg_check_elem_count()104 return -EINVAL; in soc_tplg_check_elem_count()[all …]
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6 * Copyright 2008-2022 NXP13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE227 /* Multi-Radio Configuration Group */242 /* 802.11n Configuration Group RANDYTODO for value assign */417 /** Max number of supported rates */424 #define SCAN_RSSI(RSSI) (0x100 - ((t_u8)(RSSI)))441 * @brief Sub-structure passed in wlan_ioctl_get_scan_table_entry for each BSS472 /** 0--success, 1--fail, 2--watchdogtimeout */[all …]