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/OK3568_Linux_fs/kernel/drivers/mfd/
H A Dsun6i-prcm.c74 .name = "sun6i-a31-apb0-clk",
75 .of_compatible = "allwinner,sun6i-a31-apb0-clk",
80 .name = "sun6i-a31-apb0-gates-clk",
81 .of_compatible = "allwinner,sun6i-a31-apb0-gates-clk",
92 .name = "sun6i-a31-apb0-clock-reset",
101 .name = "sun8i-a23-apb0-clk",
102 .of_compatible = "allwinner,sun8i-a23-apb0-clk",
107 .name = "sun6i-a31-apb0-gates-clk",
108 .of_compatible = "allwinner,sun8i-a23-apb0-gates-clk",
113 .name = "sun6i-a31-apb0-clock-reset",
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dallwinner,sun8i-a23-prcm.yaml30 - allwinner,sun8i-a23-apb0-clk
31 - allwinner,sun8i-a23-apb0-gates-clk
43 const: allwinner,sun8i-a23-apb0-clk
73 const: allwinner,sun8i-a23-apb0-gates-clk
174 apb0: apb0_clk {
175 compatible = "allwinner,sun8i-a23-apb0-clk";
178 clock-output-names = "apb0";
182 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
184 clocks = <&apb0>;
H A Dallwinner,sun6i-a31-prcm.yaml30 - allwinner,sun6i-a31-apb0-clk
31 - allwinner,sun6i-a31-apb0-gates-clk
41 const: allwinner,sun6i-a31-apb0-clk
71 const: allwinner,sun6i-a31-apb0-gates-clk
189 apb0: apb0_clk {
190 compatible = "allwinner,sun6i-a31-apb0-clk";
193 clock-output-names = "apb0";
197 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
199 clocks = <&apb0>;
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sun8i-apb0.c6 * Allwinner A23 APB0 clock driver
8 * Based on clk-sun6i-apb0.c
9 * Allwinner A31 APB0 clock driver
36 /* The A23 APB0 clock is a standard 2 bit wide divider clock */ in sun8i_a23_apb0_register()
68 pr_err("Could not get registers for a23-apb0-clk\n"); in sun8i_a23_apb0_setup()
84 CLK_OF_DECLARE_DRIVER(sun8i_a23_apb0, "allwinner,sun8i-a23-apb0-clk",
104 { .compatible = "allwinner,sun8i-a23-apb0-clk" },
110 .name = "sun8i-a23-apb0-clk",
H A DMakefile26 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun8i-apb0.o
29 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN6I) += clk-sun6i-apb0.o
30 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN6I) += clk-sun6i-apb0-gates.o
33 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN8I) += clk-sun8i-apb0.o
34 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN8I) += clk-sun6i-apb0-gates.o
H A Dclk-simple-gates.c95 CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
101 CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
105 CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
115 CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
127 CLK_OF_DECLARE(sun8i_a83t_apb0, "allwinner,sun8i-a83t-apb0-gates-clk",
135 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
H A Dclk-sun6i-apb0.c7 * Allwinner A31 APB0 clock driver
16 * The APB0 clk has a configurable divisor.
60 { .compatible = "allwinner,sun6i-a31-apb0-clk" },
66 .name = "sun6i-a31-apb0-clk",
H A Dclk-sun6i-apb0-gates.c7 * Allwinner A31 APB0 clock gates driver
31 { .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
32 { .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
96 .name = "sun6i-a31-apb0-gates-clk",
H A Dclk-sun9i-core.c217 pr_err("Could not get registers for a80-apb0-clk: %pOFn\n", in sun9i_a80_apb0_setup()
225 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-apb0-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb0-clk.yaml#
7 title: Allwinner A10 APB0 Bus Clock Device Tree Bindings
20 const: allwinner,sun4i-a10-apb0-clk
42 apb0@1c20054 {
44 compatible = "allwinner,sun4i-a10-apb0-clk";
47 clock-output-names = "apb0";
H A Dallwinner,sun4i-a10-gates-clk.yaml35 - const: allwinner,sun4i-a10-apb0-gates-clk
36 - const: allwinner,sun5i-a10s-apb0-gates-clk
37 - const: allwinner,sun5i-a13-apb0-gates-clk
38 - const: allwinner,sun7i-a20-apb0-gates-clk
39 - const: allwinner,sun9i-a80-apb0-gates-clk
40 - const: allwinner,sun8i-a83t-apb0-gates-clk
59 - const: allwinner,sun8i-h3-apb0-gates-clk
139 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
141 clocks = <&apb0>;
H A Dallwinner,sun9i-a80-apb0-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml#
7 title: Allwinner A80 APB0 Bus Clock Device Tree Bindings
21 - allwinner,sun9i-a80-apb0-clk
48 compatible = "allwinner,sun9i-a80-apb0-clk";
51 clock-output-names = "apb0";
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c122 int axi, ahb, apb0; in clock_set_pll1() local
137 apb0 = 2; /* Max 150MHz */ in clock_set_pll1()
139 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
152 apb0 = apb0 - 1; in clock_set_pll1()
165 apb0 << APB0_DIV_SHIFT | in clock_set_pll1()
176 apb0 << APB0_DIV_SHIFT | in clock_set_pll1()
H A Dclock_sun9i.c37 /* Set up dividers for AXI0 and APB0 on cluster 0: PLL1 / 2 = 204MHz */ in clock_init_safe()
50 /* APB0: 120 MHz (PLL_PERIPH0 / 8) */ in clock_init_safe()
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-sun8i-r.c54 static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
62 static SUNXI_CCU_GATE_HWS(apb0_pio_clk, "apb0-pio",
64 static SUNXI_CCU_GATE_HWS(apb0_ir_clk, "apb0-ir",
66 static SUNXI_CCU_GATE_HWS(apb0_timer_clk, "apb0-timer",
68 static SUNXI_CCU_GATE_HWS(apb0_rsb_clk, "apb0-rsb",
70 static SUNXI_CCU_GATE_HWS(apb0_uart_clk, "apb0-uart",
72 static SUNXI_CCU_GATE_HWS(apb0_i2c_clk, "apb0-i2c",
74 static SUNXI_CCU_GATE_HWS(apb0_twd_clk, "apb0-twd",
H A Dccu-sun4i-a10.c279 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
387 static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
389 static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
391 static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",
393 static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",
396 static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",
398 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
400 static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",
402 static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",
405 static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",
[all …]
H A Dccu-sun5i.c228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
297 static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
299 static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
301 static SUNXI_CCU_GATE(apb0_i2s_clk, "apb0-i2s", "apb0",
303 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
305 static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
307 static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
H A Dccu-sun9i-a80.c308 .hw.init = CLK_HW_INIT_PARENTS("apb0",
778 /* APB0 bus gates */
779 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0",
781 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0",
783 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0",
785 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0",
787 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0",
789 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0",
791 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0",
793 static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0",
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun8i-a23-a33.dtsi172 compatible = "allwinner,sun4i-a10-apb0-clk";
615 apb0: apb0_clk { label
616 compatible = "allwinner,sun8i-a23-apb0-clk";
619 clock-output-names = "apb0";
623 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
625 clocks = <&apb0>;
H A Dsun8i-h3.dtsi113 apb0: apb0_clk { label
119 clock-output-names = "apb0";
123 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
127 clocks = <&apb0>;
H A Dsun9i-a80.dtsi241 apb0: clk@06000070 { label
243 compatible = "allwinner,sun9i-a80-apb0-clk";
246 clock-output-names = "apb0";
350 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
352 clocks = <&apb0>;
398 compatible = "allwinner,sun8i-a23-apb0-clk";
H A Dsun6i-a31.dtsi287 compatible = "allwinner,sun4i-a10-apb0-clk";
1073 apb0: apb0_clk { label
1074 compatible = "allwinner,sun6i-a31-apb0-clk";
1077 clock-output-names = "apb0";
1081 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1083 clocks = <&apb0>;
H A Dsun5i-a10s.dtsi124 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
126 clocks = <&apb0>;
H A Dsun5i.dtsi213 apb0: apb0@01c20054 { label
215 compatible = "allwinner,sun4i-a10-apb0-clk";
218 clock-output-names = "apb0";
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsun8i-a23-a33.dtsi749 apb0: apb0_clk { label
750 compatible = "allwinner,sun8i-a23-apb0-clk";
753 clock-output-names = "apb0";
757 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
759 clocks = <&apb0>;

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