Searched +full:ahb +full:- +full:addr +full:- +full:masks (Results 1 – 8 of 8) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 The STM32 MDMA is a general-purpose direct memory access controller capable of13 described in the dma.txt file, using a five-cell specifier for each channel:22 -bit 0-1: Source increment mode26 -bit 2-3: Destination increment mode30 -bit 8-9: Source increment offset size32 0x1: half-word (16bit)[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later16 #include <linux/aspeed-lpc-ctrl.h>18 #define DEVICE_NAME "aspeed-lpc-ctrl"39 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()46 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()47 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()49 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()50 return -EINVAL; in aspeed_lpc_ctrl_mmap()52 /* ast2400/2500 AHB accesses are not cache coherent */ in aspeed_lpc_ctrl_mmap()55 if (remap_pfn_range(vma, vma->vm_start, in aspeed_lpc_ctrl_mmap()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */83 /* EP ACK/NACK IRQ masks */107 * per-device register definitions *146 * per-endpoint register definitions *213 #define AST_VHUB_NUM_GEN_EPs 15 /* Generic non-0 EPs */233 /* A transfer request, either core-originated or internal */242 * Desc number of the final packet or -1. For non-desc315 /* Index in global pool (zero-based) */345 /* Device index (zero-based) and name string */402 /* Per-port info */[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>10 * Inspired by stm32-dma.c and dma-jz4780.c16 #include <linux/dma-mapping.h>33 #include "virt-dma.h"36 #define STM32_MDMA_SHIFT(n) (ffs(n) - 1)285 return container_of(chan->vchan.chan.device, struct stm32_mdma_device, in stm32_mdma_get_dev()301 return &chan->vchan.chan.dev->device; in chan2dev()306 return mdma_dev->ddev.dev; in mdma2dev()311 return readl_relaxed(dmadev->base + reg); in stm32_mdma_read()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Copyright (c) 2010 ST-Ericsson SA27 * - CH_CONFIG register at different offset,28 * - separate CH_CONTROL2 register for transfer size,29 * - bigger maximum transfer size,30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,31 * - no support for peripheral flow control.45 * (Bursts are irrelevant for mem to mem transfers - there are no burst46 * signals, the DMA controller will simply facilitate its AHB master.)51 * - DMAC flow control: the transfer size defines the number of transfers[all …]
9 * SPDX-License-Identifier: GPL-2.0+82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */106 * 0x0008: Auto-negotiation support110 /* TX BD status masks */122 u32 nwctrl; /* 0x0 - Network Control reg */123 u32 nwcfg; /* 0x4 - Network Config reg */124 u32 nwsr; /* 0x8 - Network Status reg */126 u32 dmacr; /* 0x10 - DMA Control reg */127 u32 txsr; /* 0x14 - TX Status reg */128 u32 rxqbase; /* 0x18 - RX Q Base address reg */[all …]
2 * Misc utility routines for accessing chip-specific features14 * <<Broadcom-WL-IPTag/Proprietary:>>28 #define NCI_BAD_INDEX -1 /* Bad Index */34 #define COREINFO_COREID_MASK 0x00000FFFu /* Bit-11 to 0 */36 #define COREINFO_REV_SHIFT 12u /* Bit-12 */38 #define COREINFO_MFG_SHIFT 20u /* Bit-20 */39 #define COREINFO_BPID_MASK 0x07000000u /* 26-24 Gives Backplane ID */40 #define COREINFO_BPID_SHIFT 24u /* Bit:26-24 */46 #define IC_IFACECNT_SHIFT 12u /* Bit-12 */52 /* Interface Descriptor Masks */[all …]
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