Home
last modified time | relevance | path

Searched +full:zynq +full:- +full:7000 (Results 1 – 25 of 41) sorted by relevance

12

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dxilinx.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Platforms Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
20 - items:
21 - enum:
22 - adapteva,parallella
23 - digilent,zynq-zybo
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.zynq2 # Xilinx ZYNQ U-Boot
6 # SPDX-License-Identifier: GPL-2.0+
11 This document describes the information about Xilinx Zynq U-Boot -
14 2. Zynq boards
16 Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
25 - zc770-xm010 (single qspi, gem0, mmc)
26 - zc770-xm011 (8 or 16 bit nand)
27 - zc770-xm012 (nor)
28 - zc770-xm013 (dual parallel qspi, gem1)
38 Zynq has a facility to read the bootmode from the slcr bootmode register
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynq-picozed.dts6 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
9 #include "zynq-7000.dtsi"
12 model = "Zynq PicoZed Board";
13 compatible = "xlnx,zynq-picozed", "xlnx,zynq-7000";
28 u-boot,dm-pre-reloc;
33 u-boot,dm-pre-reloc;
38 u-boot,dm-pre-reloc;
H A Dzynq-zc770-xm011.dts6 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
9 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
13 model = "Xilinx Zynq";
23 stdout-path = "serial0:115200n8";
32 compatible = "usb-nop-xceiv";
33 #phy-cells = <0>;
43 clock-frequency = <400000>;
53 num-cs = <4>;
[all …]
H A Dzynq-zc770-xm012.dts4 * Copyright (C) 2013 - 2015 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
9 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
13 model = "Xilinx Zynq";
24 stdout-path = "serial0:115200n8";
39 clock-frequency = <400000>;
49 clock-frequency = <400000>;
59 num-cs = <4>;
[all …]
H A Dzynq-zybo.dts4 * Copyright (C) 2011 - 2015 Xilinx
7 * SPDX-License-Identifier: GPL-2.0+
9 /dts-v1/;
10 #include "zynq-7000.dtsi"
13 model = "Zynq ZYBO Development Board";
14 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
30 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
36 reset-gpios = <&gpio0 46 1>;
[all …]
H A Dzynq-microzed.dts4 * Copyright (C) 2013 - 2016 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
9 #include "zynq-7000.dtsi"
12 model = "Zynq MicroZED Board";
13 compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
32 compatible = "usb-nop-xceiv";
33 #phy-cells = <0>;
38 ps-clk-frequency = <33333333>;
[all …]
H A Dzynq-zed.dts4 * Copyright (C) 2011 - 2015 Xilinx
7 * SPDX-License-Identifier: GPL-2.0+
9 /dts-v1/;
10 #include "zynq-7000.dtsi"
13 model = "Zynq Zed Development Board";
14 compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
30 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
40 ps-clk-frequency = <33333333>;
[all …]
H A Dzynq-zc770-xm013.dts6 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
9 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
13 model = "Xilinx Zynq";
25 stdout-path = "serial0:115200n8";
40 phy-mode = "rgmii-id";
41 phy-handle = <&ethernet_phy>;
43 ethernet_phy: ethernet-phy@7 {
50 clock-frequency = <400000>;
[all …]
H A Dzynq-zc770-xm010.dts4 * Copyright (C) 2013 - 2015 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
9 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
13 model = "Xilinx Zynq";
25 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
45 phy-mode = "rgmii-id";
[all …]
H A Dzynq-7000.dtsi2 * Xilinx Zynq 7000 DTSI
3 * Describes the hardware common to all Zynq 7000-based boards.
5 * Copyright (C) 2011 - 2015 Xilinx
7 * SPDX-License-Identifier: GPL-2.0+
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "xlnx,zynq-7000";
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
[all …]
H A Dzynq-topic-miami.dts4 * Copyright (C) 2014-2016 Topic Embedded Products
6 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
9 #include "zynq-7000.dtsi"
12 model = "Topic Miami Zynq Board";
13 compatible = "topic,miami", "xlnx,zynq-7000";
31 stdout-path = "serial0:115200n8";
36 u-boot,dm-pre-reloc;
38 is-dual = <0>;
39 num-cs = <1>;
[all …]
H A Dzynq-zturn-myir.dts5 * Based on zynq-zed.dts which is:
6 * Copyright (C) 2011 - 2014 Xilinx
18 /dts-v1/;
19 /include/ "zynq-7000.dtsi"
22 model = "Zynq Z-Turn MYIR Board";
23 compatible = "xlnx,zynq-7000";
39 stdout-path = "serial0:115200n8";
42 gpio-leds {
43 compatible = "gpio-leds";
47 default-state = "on";
[all …]
/OK3568_Linux_fs/buildroot/board/zynqmp/patches/uboot/
H A D0004-arm-arm64-zynq-zynqmp-pass-the-PS-init-file-as-a-kco.patch4 Subject: [PATCH] arm/arm64: zynq/zynqmp: pass the PS init file as a kconfig
7 U-Boot needs to link ps7_init_gpl.c on Zynq or psu_init_gpl.c on
11 1. if a board-specific file exists in
12 board/xilinx/zynq[mp]/$(CONFIG_DEFAULT_DEVICE_TREE)/ps?_init_gpl.c
14 2. otherwise use board/xilinx/zynq/ps?_init_gpl.c
16 In the latter case the file does not exist in the U-Boot sources and
20 board-specific file is _not_ found (and used) requires some trickery
22 meta-xilinx yocto layer [0]).
26 * if the source tree is shared among different out-of-tree builds,
28 * the source tree cannot be read-only
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dzynq-zed.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
26 stdout-path = "serial0:115200n8";
30 compatible = "usb-nop-xceiv";
31 #phy-cells = <0>;
36 ps-clk-frequency = <33333333>;
41 phy-mode = "rgmii-id";
[all …]
H A Dzynq-zybo-z7.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "zynq-7000.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
8 compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
22 stdout-path = "serial0:115200n8";
25 gpio-leds {
26 compatible = "gpio-leds";
29 label = "zynq-zybo-z7:green:ld4";
35 #phy-cells = <0>;
[all …]
H A Dzynq-zturn.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Based on zynq-zed.dts which is:
7 * Copyright (C) 2011 - 2014 Xilinx
12 /dts-v1/;
13 /include/ "zynq-7000.dtsi"
16 model = "Zynq Z-Turn MYIR Board";
17 compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
32 stdout-path = "serial0:115200n8";
35 gpio-leds {
36 compatible = "gpio-leds";
[all …]
H A Dzynq-microzed.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 /include/ "zynq-7000.dtsi"
11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
25 stdout-path = "serial0:115200n8";
29 compatible = "usb-nop-xceiv";
30 #phy-cells = <0>;
35 ps-clk-frequency = <33333333>;
40 phy-mode = "rgmii-id";
[all …]
H A Dzynq-zybo.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
26 stdout-path = "serial0:115200n8";
30 #phy-cells = <0>;
31 compatible = "usb-nop-xceiv";
32 reset-gpios = <&gpio0 46 1>;
37 ps-clk-frequency = <50000000>;
[all …]
H A Dzynq-zc770-xm011.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
22 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
42 clock-frequency = <400000>;
52 num-cs = <4>;
[all …]
H A Dzynq-zc770-xm012.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
38 clock-frequency = <400000>;
48 clock-frequency = <400000>;
58 num-cs = <4>;
59 is-decoded-cs = <0>;
H A Dzynq-cc108.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2018 Xilinx, Inc.
6 * (C) Copyright 2007-2013 Michal Simek
7 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
11 /dts-v1/;
12 /include/ "zynq-7000.dtsi"
16 compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
25 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
[all …]
H A Dzynq-zc770-xm013.dts1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
38 phy-mode = "rgmii-id";
39 phy-handle = <&ethernet_phy>;
41 ethernet_phy: ethernet-phy@7 {
43 device_type = "ethernet-phy";
49 clock-frequency = <400000>;
[all …]
H A Dzynq-parallella.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Derived from zynq-zed.dts:
11 /dts-v1/;
12 /include/ "zynq-7000.dtsi"
16 compatible = "adapteva,parallella", "xlnx,zynq-7000";
30 stdout-path = "serial0:115200n8";
35 fclk-enable = <0xf>;
36 ps-clk-frequency = <33333333>;
41 phy-mode = "rgmii-id";
42 phy-handle = <&ethernet_phy>;
[all …]
H A Dzynq-zc770-xm010.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
32 compatible = "usb-nop-xceiv";
33 #phy-cells = <0>;
43 phy-mode = "rgmii-id";
44 phy-handle = <&ethernet_phy>;
[all …]

12