Searched full:sdrams (Results 1 – 8 of 8) sorted by relevance
206 * the SDRAMs within their permissible period. The refresh period is256 * The clock could be going away for some time. Set the SDRAMs in sa1110_target()
18 for DDR3L and LPDDR3 SDRAMs.
35 SDRAMs.
4 asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
140 /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ in pxa2xx_dram_init()
60 * 01=7.8usec (256Mbit SDRAMs)
1270 /* compatible to older SDRAMs */
1894 /* Full reset sdrams, this also re-inits the MDLL */ in radeon_reinitialize_M10()2126 /* Full reset sdrams, this also re-inits the MDLL */ in radeon_reinitialize_M9P()