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/OK3568_Linux_fs/u-boot/board/freescale/m54418twr/
H A Dm54418twr.c39 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
58 out_be32(&sdram->rcrcr, 0x40000000); in dram_init()
59 out_be32(&sdram->padcr, 0x01030203); in dram_init()
61 out_be32(&sdram->cr00, 0x01010101); in dram_init()
62 out_be32(&sdram->cr01, 0x00000101); in dram_init()
63 out_be32(&sdram->cr02, 0x01010100); in dram_init()
64 out_be32(&sdram->cr03, 0x01010000); in dram_init()
65 out_be32(&sdram->cr04, 0x00010101); in dram_init()
66 out_be32(&sdram->cr06, 0x00010100); in dram_init()
67 out_be32(&sdram->cr07, 0x00000001); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_mc_static.h12 {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
14 {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
17 {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
18 /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
19 {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
22 {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
24 {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
27 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
28 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
29 {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_immap.h34 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
35 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
36 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
37 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
38 u32 sdram_cfg; /* SDRAM Control Configuration */
39 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
40 u32 sdram_mode; /* SDRAM Mode Configuration */
41 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
42 u32 sdram_md_cntl; /* SDRAM Mode Control */
43 u32 sdram_interval; /* SDRAM Interval Configuration */
[all …]
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dsa1110-cpufreq.c8 * 7 - SDRAM auto-power-up failure (rev A0)
10 * SDRAM reads (rev A0, B0, B1)
14 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
144 struct sdram_params *sdram) in sdram_calculate_timing() argument
152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
158 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) || in sdram_calculate_timing()
164 twr = ns_to_cycles(sdram->twr, mem_khz); in sdram_calculate_timing()
167 trp = ns_to_cycles(sdram->trp, mem_khz) - 1; in sdram_calculate_timing()
173 sd->mdcnfg |= sdram->cas_latency << 12; in sdram_calculate_timing()
174 sd->mdcnfg |= sdram->cas_latency << 28; in sdram_calculate_timing()
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/ram/
H A Dst,stm32-fmc.txt8 on-board sdram memory attributes:
9 - st,sdram-control : parameters for sdram configuration, in this order:
18 - st,sdram-timing: timings for sdram, in this order:
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
43 /* sdram memory configuration from sdram datasheet */
45 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
47 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
51 /* sdram memory configuration from sdram datasheet */
53 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
55 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
/OK3568_Linux_fs/kernel/drivers/edac/
H A Daltera_edac.h14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
48 /* SDRAM Controller DRAM Status Register Bit Masks */
53 /* SDRAM Controller DRAM IRQ Register */
56 /* SDRAM Controller DRAM IRQ Register Bit Masks */
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/altera/
H A Dsdram.c11 #include <asm/arch/sdram.h>
18 u32 sdram_start; /* SDRAM start address */
19 u32 sdram_end; /* SDRAM end address */
20 u32 rule; /* SDRAM protection rule number: 0-19 */
37 * @cfg: SDRAM controller configuration data
39 * SDRAM Failure happens when accessing non-existent memory. Artificially
45 /* Define constant for 4G memory - used for SDRAM errata workaround */ in get_errata_rows()
88 printf("SDRAM workaround failed, bits set %d\n", bits); in get_errata_rows()
93 printf("SDRAM workaround rangecheck failed, %lld\n", newrows); in get_errata_rows()
102 printf("SDRAM workaround failed, newrows %lld\n", newrows); in get_errata_rows()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m5373evb/
H A Dm5373evb.c27 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
38 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
39 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
40 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
43 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
46 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
47 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
52 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
55 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
56 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m5329evb/
H A Dm5329evb.c27 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
38 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
39 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
40 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
43 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
46 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
47 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
52 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
55 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
56 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m5208evbe/
H A Dm5208evbe.c27 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
38 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
40 out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
42 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
43 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
48 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
52 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
53 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
57 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
59 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m53017evb/
H A Dm53017evb.c27 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
38 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
40 out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
42 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
43 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
48 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
52 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
53 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
57 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
59 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m54451evb/
H A Dm54451evb.c39 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
45 if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) && in dram_init()
46 (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2)) in dram_init()
57 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
59 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
60 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
65 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
69 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
71 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
75 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-orion5x/
H A Dlowlevel_init.S15 * Configuration values for SDRAM access setup
87 /*DDR SDRAM Initialization Control */
108 /* 1) Configure SDRAM */
112 /* 2) Set SDRAM Control reg */
116 /* 3) Write SDRAM address control register */
120 /* 4) Write SDRAM bank 0 size register */
125 /* 5) Write SDRAM open pages control register */
129 /* 6) Write SDRAM timing Low register */
133 /* 7) Write SDRAM timing High register */
137 /* 8) Write SDRAM mode register */
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m52277evb/
H A Dm52277evb.c35 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
49 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
51 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
52 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
55 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
59 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); in dram_init()
61 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD); in dram_init()
67 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
71 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
73 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m548xevb/
H A Dm548xevb.c29 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
56 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
57 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
60 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
63 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
64 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
69 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
72 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
73 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
75 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m547xevb/
H A Dm547xevb.c29 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
56 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
57 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
60 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
63 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
64 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
69 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
72 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
73 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
75 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S21 /* Configure the SDRAM based on the supplied settings.
23 * Input: r0 - SDRAM DEVCFG register
24 * r2 - configuration for SDRAM chips
29 /* Program the SDRAM device configuration register. */
69 /* Delay for at least 80 SDRAM clock cycles. */
86 /* Program the mode register on the SDRAM by performing fake read */
97 * Test to see if the SDRAM has been configured in a usable mode.
99 * Input: r0 - Test address of SDRAM
104 /* Load the test patterns to be written to SDRAM. */
110 /* Store the test patterns to SDRAM. */
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/include/mach/
H A Dsmemc.h15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
30 #define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
52 #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
53 #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
54 #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
55 #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
58 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
59 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m5235evb/
H A Dm5235evb.c27 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
33 * the port-size of SDRAM. In this case it is necessary to enable in dram_init()
40 /* Initialize PAR to enable SDRAM signals */ in dram_init()
53 if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) { in dram_init()
57 out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | in dram_init()
62 out_be32(&sdram->dacr0, in dram_init()
69 out_be32(&sdram->dmr0, in dram_init()
74 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); in dram_init()
85 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); in dram_init()
93 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS); in dram_init()
[all …]
/OK3568_Linux_fs/kernel/include/soc/at91/
H A Dat91sam9_sdramc.h8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
15 /* SDRAM Controller (SDRAMC) registers */
16 #define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
29 #define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
56 #define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
70 #define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
71 #define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
72 #define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
73 #define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
[all …]
/OK3568_Linux_fs/u-boot/board/Synology/ds109/
H A Dopenocd.cfg44 mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
46 mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
47 mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
48 mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
49 mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
50 mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
51 mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
52 mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
63 mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
64 mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/sh7785lcr/
H A DREADME.sh7785lcr11 - DDR2-SDRAM 512MB
28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
45 address mode. This mode can use 128MB DDR-SDRAM.
48 extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
49 "pmb" command, this mode can use 512MB DDR-SDRAM.
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
59 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
64 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-sdram-controller.txt1 Device Tree bindings for MVEBU SDRAM controllers
3 The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
8 Armada XP SDRAM controller.
12 - compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
14 include all SDRAM controller registers as per the datasheet.
19 compatible = "marvell,armada-xp-sdram-controller";
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/
H A Dsdram.su
/OK3568_Linux_fs/u-boot/tpl/arch/arm/mach-rockchip/
H A Dsdram.su

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