| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-s3c2443.c | 115 GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
174 ALIAS(SCLK_I2S0, NULL, "i2s-if"),
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| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | s3c2443.h | 32 #define SCLK_I2S0 18 macro
|
| H A D | rk3188-cru-common.h | 31 #define SCLK_I2S0 75 macro
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| H A D | rk3228-cru.h | 27 #define SCLK_I2S0 80 macro
|
| H A D | rk3128-cru.h | 28 #define SCLK_I2S0 80 macro
|
| H A D | rv1108-cru.h | 25 #define SCLK_I2S0 75 macro
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| H A D | rk3328-cru.h | 30 #define SCLK_I2S0 41 macro
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| H A D | rk3288-cru.h | 37 #define SCLK_I2S0 82 macro
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/ |
| H A D | rockchip-i2s.yaml | 118 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
|
| /OK3568_Linux_fs/u-boot/include/dt-bindings/clock/ |
| H A D | rk3188-cru-common.h | 32 #define SCLK_I2S0 75 macro
|
| H A D | rk3228-cru.h | 27 #define SCLK_I2S0 80 macro
|
| H A D | rk3128-cru.h | 28 #define SCLK_I2S0 80 macro
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| H A D | rv1108-cru.h | 25 #define SCLK_I2S0 75 macro
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| H A D | rk3288-cru.h | 35 #define SCLK_I2S0 82 macro
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| H A D | rk3328-cru.h | 30 #define SCLK_I2S0 41 macro
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 549 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
673 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3128.c | 359 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
|
| H A D | clk-rk3228.c | 425 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
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| H A D | clk-rv1108.c | 509 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | rk3128.dtsi | 93 clocks = <&cru PCLK_ACODEC>, <&cru SCLK_I2S0>;
|
| H A D | rk3288-firefly-reload.dts | 223 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|
| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | rk3288-veyron-mickey.dts | 190 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
|
| H A D | .rk3288-veyron-mickey.dtb.pre.tmp | |
| H A D | rk3188.dtsi | 84 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|
| H A D | rk3066a.dtsi | 71 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|