xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip Clock Out Control Module Binding
8
9maintainers:
10  - Sugar Zhang <sugar.zhang@rock-chips.com>
11
12description: |
13  This add support switch for clk-bidirection which located
14  at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
15  and these config maybe located in many pieces of GRF,
16  which hard to addressed in one single clk driver. so, we add
17  this simple helper driver to address this situation.
18
19  In order to simplify implement and usage, and also for safety
20  clk usage (avoid high freq glitch), we set all clk out as disabled
21  (which means Input default for clk-bidrection) in the pre-stage,
22  such boot-loader or init by HW default. And then set a safety freq
23  before enable clk-out, such as "assign-clock-rates" or clk_set_rate
24  in drivers.
25
26properties:
27  compatible:
28    enum:
29      - rockchip,clk-out
30
31  reg:
32    maxItems: 1
33
34  "#clock-cells":
35    const: 1
36
37  clocks:
38    maxItems: 1
39    description: parent clocks.
40
41  power-domains:
42    maxItems: 1
43
44  clock-output-names:
45    maxItems: 1
46
47  rockchip,bit-shift:
48    $ref: /schemas/types.yaml#/definitions/uint32
49    description: Defines the bit shift of clk out enable.
50
51  rockchip,bit-set-to-disable:
52    type: boolean
53    description: |
54      By default this clock sets the bit at bit-shift to enable the clock.
55      Setting this property does the opposite: setting the bit disable
56      the clock and clearing it enables the clock.
57
58required:
59  - compatible
60  - reg
61  - clocks
62  - "#clock-cells"
63  - clock-output-names
64  - rockchip,bit-shift
65
66additionalProperties: false
67
68examples:
69  # Clock Provider node:
70  - |
71    mclkin_sai0: mclkin-sai0 {
72        compatible = "fixed-clock";
73        #clock-cells = <0>;
74        clock-frequency = <12288000>;
75        clock-output-names = "mclk_sai0_from_io";
76    };
77
78    mclkout_sai0: mclkout-sai0@ff040070 {
79        compatible = "rockchip,clk-out";
80        reg = <0 0xff040070 0 0x4>;
81        clocks = <&cru MCLK_SAI0_OUT2IO>;
82        #clock-cells = <0>;
83        clock-output-names = "mclk_sai0_to_io";
84        rockchip,bit-shift = <4>;
85    };
86
87  # Clock mclkout Consumer node:
88  - |
89    ext_codec {
90        clocks = <&mclkout_sai0>;
91        clock-names = "mclk";
92        assigned-clocks = <&mclkout_sai0>;
93        assigned-clock-rates = <12288000>;
94        pinctrl-names = "default";
95        pinctrl-0 = <&i2s0m0_mclk>;
96    };
97
98  # Clock mclkin Consumer node:
99  - |
100    ext_codec {
101        clocks = <&mclkin_sai0>;
102        clock-names = "mclk";
103        assigned-clocks = <&cru CLK_SAI0>;
104        assigned-clock-parents = <&mclkin_sai0>;
105        pinctrl-names = "default";
106        pinctrl-0 = <&i2s0m0_mclk>;
107    };
108