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Searched full:jz4740_clk_pll_half (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/ingenic/
H A Djz4740-cgu.c94 [JZ4740_CLK_PLL_HALF] = {
141 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
157 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
173 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
180 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
187 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Djz4740-cgu.h18 #define JZ4740_CLK_PLL_HALF 3 macro
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dingenic,aic.yaml87 <&cgu JZ4740_CLK_PLL_HALF>;
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi198 <&cgu JZ4740_CLK_PLL_HALF>;