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33 * a) initialise a dm_array_info structure. This describes the array65 * Describes an array. Don't initialise this structure yourself, use the80 * vt - describes the leaf values.89 * info - describes the array97 * info - describes the array123 * info - describes the array142 * info - describes the array155 * info - describes the array174 * info - describes the array
29 * This describes the bitset and includes the cache. It's not called it90 * info - describes the bitset101 * info - describes the array114 * info - describes the bitset133 * info - describes the bitset146 * info - describes the bitset159 * info - describes the bitset173 * info - describes the bitset
46 describes the acknowledge line from vcxk hardware49 describes the enable line to vcxk hardware52 describes the invert line to vcxk hardware55 describes the reset line to vcxk hardware58 describes the request line to vcxk hardware
... A></STRONG> 111 112- This describes <STRONG>ncurses</STRONG> version 6.1 ...
1# ncurses 6.1 - patch 20190713 - Thomas E. Dickey 2# 3# --- ...
... A></STRONG> 128 129- This describes <STRONG>ncurses</STRONG> version 6.1 ...
33 // This describes the components of the system.82 // This describes an error and it's likely causes.92 // This describes ECC errors.100 // This describes miscompare errors.108 // This describes HDD miscompare errors.116 // This describes HDD miscompare errors.
12 This device tree binding describes CPU features available to software, with104 This property describes the privilege levels and/or software components118 This property describes the HV privilege support required to enable the137 This property describes the OS privilege support required to enable the154 property describes the bit number in the HFSCR register that the167 property describes the bit number in the FSCR register that the180 This property describes the bit number that should be set in the ELF AUX
26 Describes the main PLL clock output (before POSTDIV). The node name must33 Describes the PLLDIVn divider clocks that provide the SYSCLKn clock41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".
21 * This structure describes address space window. Window base can be30 /* This structure describes SoC units address decode window */39 * This enumerator describes the type of functionality the XOR channel56 * This enumerator describes the set of commands that can be applied on
23 /* We keep linked lists of DU_HEAD structures, each of which describes34 /* Describes the register being tracked. */64 /* This struct describes a single occurrence of a register. */78 /* This struct describes data gathered during regrename_analyze about
30 A "cpu" node describes one logical processor (hardware thread).44 This node describes the in-core peripherals. Required property:49 This node describes the PCI bus on the SoC. Its property should be
17 * struct imx1_pin - describes an IMX1/21/27 pin.29 * struct imx1_pin_group - describes an IMX pin group43 * struct imx1_pmx_func - describes IMX pinmux functions
15 * This enumerator describes the type of functionality the XOR channel25 * This enumerator describes the set of commands that can be applied on41 * This enumerator describes the set of state conditions.
64 This property describes the bitfields used to control the state of devices.65 Each tuple describes a range of identical bitfields used to control one or80 This property describes the bitfields used to provide device state status81 for device states controlled by the DSCR. Each tuple describes a range of
29 * Describes the size of the image buffer45 * Describes the pixel width stride of the image buffer47 * Describes the pixel height stride of the image buffer49 * Describes the pixel format of the image buffer
82 * @chp_info: Describes client chipset device and driver.83 * @bus_info: Describes client bus device and driver.84 * @dev_info: Describes client device and driver for each device on the
9 first level describes the ethernet controller itself and the second level10 describes up to 3 ethernet port nodes within that controller. The reason for12 set of controller registers. Each port node describes port-specific properties.
6 differences. Hence, this document describes closely related but different30 Tegra HW documentation describes a unified naming convention for all GPIOs43 describes the port-level mapping. In that file, the naming convention for ports90 order the HW manual describes them. The number of entries required varies
6 differences. Hence, this document describes closely related but different30 Tegra HW documentation describes a unified naming convention for all GPIOs43 describes the port-level mapping. In that file, the naming convention for ports92 order the HW manual describes them. The number of entries required varies
53 This entry describes the BCR of the master controller driving63 This entry describes the DCR of the master controller driving75 This entry describes the PID of the master controller driving88 This entry describes the HDRCAP of the master controller