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/OK3568_Linux_fs/u-boot/board/micronas/vct/vctv/
H A Dreg_ebi.h17 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
19 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
21 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
23 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
25 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
27 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
29 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
31 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
33 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
35 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
[all …]
/OK3568_Linux_fs/u-boot/board/micronas/vct/vcth2/
H A Dreg_ebi.h17 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
19 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
21 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
23 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
25 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
27 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
29 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
31 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
33 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
35 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
[all …]
/OK3568_Linux_fs/u-boot/board/micronas/vct/vcth/
H A Dreg_ebi.h17 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
19 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
21 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
23 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
25 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
27 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
29 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
31 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) argument
33 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) argument
35 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dpearl_pcie_regs.h8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) argument
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) argument
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) argument
11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14) argument
12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18) argument
13 #define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c) argument
14 #define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20) argument
15 #define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24) argument
16 #define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28) argument
17 #define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c) argument
[all …]
/OK3568_Linux_fs/external/rknn-toolkit2/packages/
H A Drknn_toolkit2-1.5.0+1fa95b5c-cp310-cp310-linux_x86_64.whl ... -x86_64-linux-gnu.so rknn/base/convertor/tensorflow2onnx/VERSION_NUMBER rknn/base/
H A Drknn_toolkit2-1.5.0+1fa95b5c-cp38-cp38-linux_x86_64.whl ... -x86_64-linux-gnu.so rknn/base/convertor/tensorflow2onnx/VERSION_NUMBER rknn/base/ ...
H A Drknn_toolkit2-1.5.0+1fa95b5c-cp36-cp36m-linux_x86_64.whl ... -x86_64-linux-gnu.so rknn/base/convertor/tensorflow2onnx/VERSION_NUMBER rknn/base/
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx7d.c383 void __iomem *base; in imx7d_clocks_init() local
398 base = of_iomap(np, 0); in imx7d_clocks_init()
399 WARN_ON(!base); in imx7d_clocks_init()
402 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
406 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
407 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
409 …hws[IMX7D_PLL_ARM_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7… in imx7d_clocks_init()
[all …]
H A Dclk-imx6ul.c117 void __iomem *base; in imx6ul_clocks_init() local
137 base = of_iomap(np, 0); in imx6ul_clocks_init()
139 WARN_ON(!base); in imx6ul_clocks_init()
141 …hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
142 …hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
143 …hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
144 …hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
145 …hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
146 …hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
147 …hws[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
[all …]
H A Dclk-imx6sll.c82 void __iomem *base; in imx6sll_clocks_init() local
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
107 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
108 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
109 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
110 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
111 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70)); in imx6sll_clocks_init()
112 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0)); in imx6sll_clocks_init()
113 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0)); in imx6sll_clocks_init()
[all …]
H A Dclk-imx6sx.c123 void __iomem *base; in imx6sx_clocks_init() local
147 base = of_iomap(np, 0); in imx6sx_clocks_init()
148 WARN_ON(!base); in imx6sx_clocks_init()
151 …hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
152 …hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
153 …hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
154 …hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
155 …hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
156 …hws[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
157 …hws[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src… in imx6sx_clocks_init()
[all …]
H A Dclk-imx6sl.c184 void __iomem *base; in imx6sl_clocks_init() local
202 base = of_iomap(np, 0); in imx6sl_clocks_init()
203 WARN_ON(!base); in imx6sl_clocks_init()
205 anatop_base = base; in imx6sl_clocks_init()
207 …hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
208 …hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
209 …hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
210 …hws[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
211 …hws[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
212 …hws[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
[all …]
H A Dclk-imx8mm.c298 void __iomem *base; in imx8mm_clocks_probe() local
318 base = of_iomap(np, 0); in imx8mm_clocks_probe()
320 if (WARN_ON(!base)) in imx8mm_clocks_probe()
323 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
324 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
325 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
326 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
327 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
328 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
329 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
[all …]
/OK3568_Linux_fs/external/rknn-toolkit2/docker/docker_file/ubuntu_18_04_cp36/
H A Drknn_toolkit2-1.5.0+1fa95b5c-cp36-cp36m-linux_x86_64.whl ... -x86_64-linux-gnu.so rknn/base/convertor/tensorflow2onnx/VERSION_NUMBER rknn/base/
/OK3568_Linux_fs/yocto/poky/meta/recipes-core/packagegroups/
H A Dpackagegroup-base.bb12 packagegroup-base \
13 packagegroup-base-extended \
14 packagegroup-distro-base \
15 packagegroup-machine-base \
17 ${@bb.utils.contains("MACHINE_FEATURES", "acpi", "packagegroup-base-acpi", "",d)} \
18 ${@bb.utils.contains("MACHINE_FEATURES", "alsa", "packagegroup-base-alsa", "", d)} \
19 ${@bb.utils.contains("MACHINE_FEATURES", "apm", "packagegroup-base-apm", "", d)} \
20 ${@bb.utils.contains("MACHINE_FEATURES", "ext2", "packagegroup-base-ext2", "", d)} \
21 ${@bb.utils.contains("MACHINE_FEATURES", "vfat", "packagegroup-base-vfat", "", d)} \
22 … ${@bb.utils.contains("MACHINE_FEATURES", "keyboard", "packagegroup-base-keyboard", "", d)} \
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/share/i18n/locales/
H A Ddz_BT1063 <e0f40-0f62> "<S0F40><S0F62><VRNT1><VRNT1>";"<BASE><BASE>";"<MIN><MIN>";IGNORE
1064 <e0f40-0f62-0f90> "<S0F40><S0F62><VRNT1><VRNT2>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1065 <e0f40-0f62-0f9f> "<S0F40><S0F62><VRNT1><VRNT3>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1066 <e0f40-0f62-0f9e> "<S0F40><S0F62><VRNT1><VRNT4>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1067 <e0f40-0f62-0fa8> "<S0F40><S0F62><VRNT1><VRNT5>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1068 <e0f40-0f62-0fb4> "<S0F40><S0F62><VRNT2><VRNT1>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1069 <e0f40-0f62-0fb5> "<S0F40><S0F62><VRNT2><VRNT2>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1071 <e0f40-0f63> "<S0F40><S0F63><VRNT1>";"<BASE><BASE>";"<MIN><MIN>";IGNORE
1072 <e0f40-0f63-0f90> "<S0F40><S0F63><VRNT2>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1073 <e0f40-0f63-0fa4> "<S0F40><S0F63><VRNT3>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
[all …]
H A Diso14651_t1_common88 collating-symbol <BASE>
1339 <BASE>
2532 <S21A8> % UP DOWN ARROW WITH BASE
5034 <S10137> % AEGEAN WEIGHT BASE UNIT
5052 <S10182> % GREEK KYATHOS BASE SIGN
5059 <S10189> % GREEK TRYBLION BASE SIGN
54833 % <Uxxxx> <Base>;<Accent>;<Case>;<Special>
56087 <U21A8> IGNORE;IGNORE;IGNORE;<U21A8> % UP DOWN ARROW WITH BASE
59053 <U00010137> IGNORE;IGNORE;IGNORE;<U00010137> % AEGEAN WEIGHT BASE UNIT
59115 <U00010182> IGNORE;IGNORE;IGNORE;<U00010182> % GREEK KYATHOS BASE SIGN
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/share/i18n/locales/
H A Ddz_BT1063 <e0f40-0f62> "<S0F40><S0F62><VRNT1><VRNT1>";"<BASE><BASE>";"<MIN><MIN>";IGNORE
1064 <e0f40-0f62-0f90> "<S0F40><S0F62><VRNT1><VRNT2>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1065 <e0f40-0f62-0f9f> "<S0F40><S0F62><VRNT1><VRNT3>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1066 <e0f40-0f62-0f9e> "<S0F40><S0F62><VRNT1><VRNT4>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1067 <e0f40-0f62-0fa8> "<S0F40><S0F62><VRNT1><VRNT5>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1068 <e0f40-0f62-0fb4> "<S0F40><S0F62><VRNT2><VRNT1>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1069 <e0f40-0f62-0fb5> "<S0F40><S0F62><VRNT2><VRNT2>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1071 <e0f40-0f63> "<S0F40><S0F63><VRNT1>";"<BASE><BASE>";"<MIN><MIN>";IGNORE
1072 <e0f40-0f63-0f90> "<S0F40><S0F63><VRNT2>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
1073 <e0f40-0f63-0fa4> "<S0F40><S0F63><VRNT3>";"<BASE><BASE><BASE>";"<MIN><MIN><MIN>";IGNORE
[all …]
H A Diso14651_t1_common88 collating-symbol <BASE>
1339 <BASE>
2532 <S21A8> % UP DOWN ARROW WITH BASE
5034 <S10137> % AEGEAN WEIGHT BASE UNIT
5052 <S10182> % GREEK KYATHOS BASE SIGN
5059 <S10189> % GREEK TRYBLION BASE SIGN
54833 % <Uxxxx> <Base>;<Accent>;<Case>;<Special>
56087 <U21A8> IGNORE;IGNORE;IGNORE;<U21A8> % UP DOWN ARROW WITH BASE
59053 <U00010137> IGNORE;IGNORE;IGNORE;<U00010137> % AEGEAN WEIGHT BASE UNIT
59115 <U00010182> IGNORE;IGNORE;IGNORE;<U00010182> % GREEK KYATHOS BASE SIGN
[all …]
/OK3568_Linux_fs/kernel/drivers/video/rockchip/iep/
H A Dhw_iep_reg.h377 #define IEP_REGB_V_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
378 #define IEP_REGB_H_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
379 #define IEP_REGB_SCL_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
380 #define IEP_REGB_SCL_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
381 #define IEP_REGB_SCL_UP_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
382 #define IEP_REGB_DIL_EI_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
383 #define IEP_REGB_DIL_EI_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
384 #define IEP_REGB_CON_GAM_ORDER(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
385 #define IEP_REGB_RGB_ENH_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
386 #define IEP_REGB_RGB_CON_GAM_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0… argument
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm_8960.c14 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
16 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
20 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); in dsi_28nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi5_core.c28 void __iomem *base = core->base; in hdmi5_core_ddc_init() local
43 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi5_core_ddc_init()
44 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi5_core_ddc_init()
49 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi5_core_ddc_init()
53 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi5_core_ddc_init()
55 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi5_core_ddc_init()
60 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi5_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi5_core_ddc_init()
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi5_core_ddc_init()
69 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi5_core_ddc_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi5_core.c41 void __iomem *base = core->base; in hdmi_core_ddc_init() local
56 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
57 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
68 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
75 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
80 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
82 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/s5p-jpeg/
H A Djpeg-hw-exynos4.c16 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset() argument
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
22 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode() argument
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
41 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
45 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dnsp32_io.h12 static inline void nsp32_write1(unsigned int base, in nsp32_write1() argument
16 outb(val, (base + index)); in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1() argument
22 return inb(base + index); in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2() argument
29 outw(val, (base + index)); in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2() argument
35 return inw(base + index); in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4() argument
42 outl(val, (base + index)); in nsp32_write4()
[all …]

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