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/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
44 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/
H A Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
43 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/
H A Dmac_reg.h29 #define B_AX_GT0_COUNT_EN BIT(31)
30 #define B_AX_GT0_MODE BIT(30)
31 #define B_AX_GT0_EN BIT(29)
32 #define B_AX_GT0_SORT_EN BIT(28)
41 #define B_AX_GT1_COUNT_EN BIT(31)
42 #define B_AX_GT1_MODE BIT(30)
43 #define B_AX_GT1_EN BIT(29)
44 #define B_AX_GT1_SORT_EN BIT(28)
53 #define B_AX_GT2_COUNT_EN BIT(31)
54 #define B_AX_GT2_MODE BIT(30)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/
H A Dmac_reg.h29 #define B_AX_GT0_COUNT_EN BIT(31)
30 #define B_AX_GT0_MODE BIT(30)
31 #define B_AX_GT0_EN BIT(29)
32 #define B_AX_GT0_SORT_EN BIT(28)
41 #define B_AX_GT1_COUNT_EN BIT(31)
42 #define B_AX_GT1_MODE BIT(30)
43 #define B_AX_GT1_EN BIT(29)
44 #define B_AX_GT1_SORT_EN BIT(28)
53 #define B_AX_GT2_COUNT_EN BIT(31)
54 #define B_AX_GT2_MODE BIT(30)
[all …]
/OK3568_Linux_fs/kernel/include/soc/mscc/
H A Docelot_dev.h11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
H A Docelot_hsio.h85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
109 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_regs.h15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/fw_ax/inc_hdr/
H A Dfwcmd_intf.h162 // CLASS 8 - Media Status Report
305 // CLASS 8
443 // CLASS 8 - FCS
530 // Bit definition//
537 #define FWCMD_H2CREG_H2CREG_HDR_ACK BIT(7)
538 #define FWCMD_H2CREG_H2CREG_HDR_TOTAL_LEN_SH 8
552 #define FWCMD_H2CREG_H2CREG_LB_ACK BIT(7)
553 #define FWCMD_H2CREG_H2CREG_LB_TOTAL_LEN_SH 8
563 #define FWCMD_H2CREG_CNSL_CMD_ACK BIT(7)
564 #define FWCMD_H2CREG_CNSL_CMD_TOTAL_LEN_SH 8
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/fw_ax/inc_hdr/
H A Dfwcmd_intf.h162 // CLASS 8 - Media Status Report
305 // CLASS 8
443 // CLASS 8 - FCS
530 // Bit definition//
537 #define FWCMD_H2CREG_H2CREG_HDR_ACK BIT(7)
538 #define FWCMD_H2CREG_H2CREG_HDR_TOTAL_LEN_SH 8
552 #define FWCMD_H2CREG_H2CREG_LB_ACK BIT(7)
553 #define FWCMD_H2CREG_H2CREG_LB_TOTAL_LEN_SH 8
563 #define FWCMD_H2CREG_CNSL_CMD_ACK BIT(7)
564 #define FWCMD_H2CREG_CNSL_CMD_TOTAL_LEN_SH 8
[all …]
/OK3568_Linux_fs/kernel/drivers/net/fddi/skfp/h/
H A Dskfbi.h40 #define B0_RAP 0x0000 /* 8 bit register address port */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
47 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/
H A Dtrivial-devices.yaml109 # 5 Bit Programmable, Pulse-Width Modulator
111 # 10-bit 8 channels 300ks/s SPI ADC with temperature sensor
113 # 10-bit 12 channels 300ks/s SPI ADC with temperature sensor
115 # 10-bit 16 channels 300ks/s SPI ADC with temperature sensor
117 # 12-bit 8 channels 300ks/s SPI ADC with temperature sensor
119 # 12-bit 12 channels 300ks/s SPI ADC with temperature sensor
121 # 12-bit 16 channels 300ks/s SPI ADC with temperature sensor
123 # Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
127 # 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
131 # mCube 3-axis 8-bit digital accelerometer
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/vc4/
H A Dvc4_regs.h26 ('3' << 8) | \
37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
38 # define V3D_IDENT1_QUPS_SHIFT 8
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
57 # define V3D_SLCACTL_UCC_SHIFT 8
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/ice/
H A Dice_hw_autogen.h19 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
20 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
22 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
30 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
31 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
32 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
35 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
43 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
44 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h18 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
19 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
27 #define MT_EFUSE_CTRL_KICK BIT(30)
28 #define MT_EFUSE_CTRL_SEL BIT(31)
34 #define MT_COEXCFG0_COEX_EN BIT(0)
37 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
38 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
39 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
41 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
[all …]
H A Dmac.h10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/marvell/
H A Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
195 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/v3d/
H A Dv3d_regs.h30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
37 # define V3D_HUB_IDENT1_NCORES_SHIFT 8
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
49 # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8)
50 # define V3D_HUB_IDENT3_IPREV_SHIFT 8
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/vsp1/
H A Dvsp1_regs.h18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
23 #define VI6_CLK_DCSWT_CSTPW_SHIFT 8
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
35 #define VI6_WFP_IRQ_ENB_DFEE BIT(1)
36 #define VI6_WFP_IRQ_ENB_FREE BIT(0)
39 #define VI6_WFP_IRQ_STA_DFE BIT(1)
[all …]
/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg13 # Two 8-Bit devices are connected on the 16-Bit bus on the same
22 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
23 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
24 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
25 # bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5])
26 # bit 19-16: 1, MPPSel4 NF_IO[6]
27 # bit 23-20: 1, MPPSel5 NF_IO[7]
28 # bit 27-24: 1, MPPSel6 SYSRST_O
29 # bit 31-28: 0, MPPSel7 GPO[7]
32 # bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
[all …]
H A Dkwbimage_128M16_1.cfg20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
30 # bit 3-0: 0, MPPSel8 GPIO[8]
31 # bit 7-4: 0, MPPSel9 GPIO[9]
[all …]
/OK3568_Linux_fs/kernel/drivers/gpio/
H A Dgpio-ws16c48.c36 * @io_state: bit I/O state (whether bit is set to input or output)
56 const unsigned port = offset / 8; in ws16c48_gpio_get_direction()
57 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_get_direction()
68 const unsigned port = offset / 8; in ws16c48_gpio_direction_input()
69 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_direction_input()
87 const unsigned port = offset / 8; in ws16c48_gpio_direction_output()
88 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_direction_output()
108 const unsigned port = offset / 8; in ws16c48_gpio_get()
109 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_get()
141 port_addr = ws16c48gpio->base + offset / 8; in ws16c48_gpio_get_multiple()
[all …]
/OK3568_Linux_fs/kernel/drivers/power/supply/
H A Dbd99954-charger.h482 [F_PREV_CHGSTM_STATE] = REG_FIELD(CHGSTM_STATUS, 8, 14),
486 [F_BATTEMP] = REG_FIELD(CHGOP_STATUS, 8, 10),
490 [F_THERMWDT_VAL] = REG_FIELD(WDT_STATUS, 8, 15),
513 [F_SDP_CHG_TRIG] = REG_FIELD(CHGOP_SET1, 8, 8),
520 [F_BATT_LEARN] = REG_FIELD(CHGOP_SET2, 8, 8),
530 [F_WDT_FST] = REG_FIELD(CHGWDT_SET, 8, 15),
532 [F_WDT_IBAT_SHORT] = REG_FIELD(BATTWDT_SET, 8, 15),
551 [F_PROCHOT_IDCHG_DG_SET] = REG_FIELD(PROCHOT_CTRL_SET, 8, 9),
558 [F_PMON_INSEL] = REG_FIELD(PMON_IOUT_CTRL_SET, 8, 8),
567 [F_VCC_ADCRTRY] = REG_FIELD(VCC_UCD_SET, 8, 8),
[all …]
/OK3568_Linux_fs/kernel/sound/soc/rockchip/
H A Drockchip_spdifrx.h15 #define SPDIFRX_CFGR_TWAD_STREAM BIT(1)
16 #define SPDIFRX_EN_MASK BIT(0)
17 #define SPDIFRX_EN BIT(0)
21 #define SPDIFRX_CLR_RXSC BIT(0)
25 #define SPDIFRX_CDR_AVGSEL_MASK BIT(1)
27 #define SPDIFRX_CDR_AVGSEL_AVG BIT(1)
28 #define SPDIFRX_CDR_BYPASS_MASK BIT(0)
29 #define SPDIFRX_CDR_BYPASS_EN BIT(0)
34 #define SPDIFRX_CDRST_MAXCNT_MASK GENMASK(15, 8)
38 #define SPDIFRX_DMACR_RDE_MASK BIT(5)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/stmicro/stmmac/
H A Ddwxgmac2.h28 #define XGMAC_CONFIG_JD BIT(16)
29 #define XGMAC_CONFIG_TE BIT(0)
32 #define XGMAC_CONFIG_ARPEN BIT(31)
38 #define XGMAC_CONFIG_S2KP BIT(11)
39 #define XGMAC_CONFIG_LM BIT(10)
40 #define XGMAC_CONFIG_IPC BIT(9)
41 #define XGMAC_CONFIG_JE BIT(8)
42 #define XGMAC_CONFIG_WD BIT(7)
43 #define XGMAC_CONFIG_GPSLCE BIT(6)
44 #define XGMAC_CONFIG_CST BIT(2)
[all …]

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