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/OK3568_Linux_fs/kernel/drivers/media/i2c/jaguar1_drv/
H A Djaguar1_reg_set_def.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define REG_SET_0x00_0_8_EACH_SET(ch, val) vd_register_set ( 0 , 0x00 , 0x00 + ch , val , 0 , 8 ) argument
33 #define REG_SET_0x18_0_8_EX_CBAR_ON(ch, val) vd_register_set ( 0 , 0x00 , 0x18 + ch , val , 0 , 8 ) argument
34 #define REG_SET_5x00_0_8_CMP(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x00 , val , 0 , 8 ) argument
35 #define REG_SET_5x01_0_8_CML(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x01 , val , 0 , 8 ) argument
36 #define REG_SET_5x1D_0_8_AFE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x1d , val , 0 , 8 ) argument
37 #define REG_SET_5x92_0_8_PWM(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x92 , val , 0 , 8 ) argument
40 #define REG_SET_1xEC_0_8_yc_merge(ch, val) vd_register_set ( 0 , 0x01 , 0xec + ch , val , 0 , 8 ) argument
43 #define REG_SET_1xC8_0_8_out_sel(ch, val) vd_register_set ( 0 , 0x01 , 0xc8 + ch , val , 0 , 8 ) argument
49 #define REG_SET_1x7C_0_1_clk_auto_1(ch, val) vd_register_set ( 0 , 0x01 , 0x7c , val , 0 , 1 ) argument
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/OK3568_Linux_fs/kernel/drivers/gpu/ipu-v3/
H A Dipu-cpmem.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include "ipu-prv.h"
30 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
93 ipu_get_cpmem(struct ipuv3_channel *ch) in ipu_get_cpmem() argument
95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
97 return cpmem->base + ch->num; in ipu_get_cpmem()
100 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) in ipu_ch_param_write_field() argument
102 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_write_field()
103 u32 bit = (wbs >> 8) % 160; in ipu_ch_param_write_field()
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/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dch.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (c) 1996-2003 Gerd Knorr <kraxel@bytesex.org>
38 #define CH_TYPES 8
71 static int dt_id[CH_DT_MAX] = { [ 0 ... (CH_DT_MAX-1) ] = -1 };
76 /* tell the driver about vendor-specific slots */
77 static int vendor_firsts[CH_TYPES-4];
78 static int vendor_counts[CH_TYPES-4];
82 static const char * vendor_labels[CH_TYPES-4] = {
87 #define ch_printk(prefix, ch, fmt, a...) \ argument
88 sdev_prefix_printk(prefix, (ch)->device, (ch)->name, fmt, ##a)
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/imx/dcss/
H A Ddcss-dpr.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "dcss-dev.h"
36 #define PIX_SIZE_POS 8
37 #define PIX_SIZE_MASK GENMASK(9, 8)
118 struct dcss_dpr_ch ch[3]; member
121 static void dcss_dpr_write(struct dcss_dpr_ch *ch, u32 val, u32 ofs) in dcss_dpr_write() argument
123 struct dcss_dpr *dpr = ch->dpr; in dcss_dpr_write()
125 dcss_ctxld_write(dpr->ctxld, dpr->ctx_id, val, ch->base_ofs + ofs); in dcss_dpr_write()
130 struct dcss_dpr_ch *ch; in dcss_dpr_ch_init_all() local
134 ch = &dpr->ch[i]; in dcss_dpr_ch_init_all()
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H A Ddcss-scaler.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "dcss-dev.h"
16 #define SCALE2MEM_EN BIT(8)
33 #define A2R10G10B10_FORMAT_POS 8
34 #define A2R10G10B10_FORMAT_MASK GENMASK(11, 8)
88 struct dcss_scaler_ch ch[3]; member
101 #define PSC_PHASE_MASK (PSC_NUM_PHASES - 1)
103 #define PSC_Q_ROUND_OFFSET (1 << (PSC_Q_FRACTION - 1))
106 * mult_q() - Performs fixed-point multiplication.
122 * div_q() - Performs fixed-point division.
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3308bs-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 pcfg_pull_none_0_4ma: pcfg-pull-none-0-4ma {
9 bias-disable;
10 drive-strength-s = <4>;
12 pcfg_pull_none_0_4ma_smt: pcfg-pull-none-0-4ma-smt {
13 bias-disable;
14 drive-strength-s = <4>;
15 input-schmitt-enable;
17 pcfg_pull_up_0_4ma: pcfg-pull-up-0-4ma {
18 bias-pull-up;
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/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/rapidjson/1.1.0/include/rapidjson/
H A Dencodings.h40 …typename Ch; //! Type of character. A "character" is actually a code unit in unicode's definiti…
73 static Ch Take(InputByteStream& is);
81 static void Put(OutputByteStream& os, Ch c);
89 //! UTF-8 encoding.
90 /*! http://en.wikipedia.org/wiki/UTF-8
92 \tparam CharType Code unit for storing 8-bit UTF-8 data. Default is char.
97 typedef CharType Ch; typedef
104 os.Put(static_cast<Ch>(codepoint & 0xFF)); in Encode()
106 os.Put(static_cast<Ch>(0xC0 | ((codepoint >> 6) & 0xFF))); in Encode()
107 os.Put(static_cast<Ch>(0x80 | ((codepoint & 0x3F)))); in Encode()
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/OK3568_Linux_fs/kernel/drivers/media/i2c/nvp6158_drv/
H A Dnvp6158_video_auto_detect.h1 // SPDX-License-Identifier: GPL-2.0
32 unsigned char spd; //B5/6/7/8 0x00 [5:4]
34 unsigned char ctrlreg; //B5/6/7/8 0x01 [6]
35 unsigned char ctrlibs; //B5/6/7/8 0x01 [5:4]
36 unsigned char adcspd; //B5/6/7/8 0x01 [2]
37 unsigned char clplevel; //B5/6/7/8 0x01 [1:0]
40 unsigned char eq_band; //B5/6/7/8 0x58 [6:4]
41 unsigned char lpf_front_band; //B5/6/7/8 0x58 [1:0]
43 unsigned char clpmode; //B5/6/7/8 0x59 [7]
44 unsigned char f_lpf_bypass; //B5/6/7/8 0x59 [4]
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H A Dnvp6158_video_auto_detect.c1 // SPDX-License-Identifier: GPL-2.0
135 NC_VIVO_CH_FORMATDEF NVP6158_NC_VD_AUTO_VFCtoFMTDEF(unsigned char ch, unsigned char VFC) in NVP6158_NC_VD_AUTO_VFCtoFMTDEF() argument
137 if((nvp6158_chip_id[ch/4] == NVP6168C_R0_ID) || in NVP6158_NC_VD_AUTO_VFCtoFMTDEF()
138 (nvp6158_chip_id[ch/4] == NVP6168_R0_ID)) { in NVP6158_NC_VD_AUTO_VFCtoFMTDEF()
141 if(nvp6158_det_mode[ch] == NVP6158_DET_MODE_AUTO) in NVP6158_NC_VD_AUTO_VFCtoFMTDEF()
143 else if(nvp6158_det_mode[ch] == NVP6158_DET_MODE_CVI) in NVP6158_NC_VD_AUTO_VFCtoFMTDEF()
145 else if(nvp6158_det_mode[ch] == NVP6158_DET_MODE_TVI) in NVP6158_NC_VD_AUTO_VFCtoFMTDEF()
162 gpio_i2c_write(nvp6158_iic_addr[vin_auto_det->devnum], 0xFF, 0x01); in _nvp6158_video_input_auto_detect_vafe_set()
163 val_1x7A = gpio_i2c_read(nvp6158_iic_addr[vin_auto_det->devnum], 0x7A); in _nvp6158_video_input_auto_detect_vafe_set()
164 val_1x7A |= (1 << vin_auto_det->ch); in _nvp6158_video_input_auto_detect_vafe_set()
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
52 #define PHY_CA_DRV_SHIFT 8
62 #define PHY_ODT_SHIFT 8
78 #define PHY_CA_SR_SHIFT 8
102 #define PHY_LP4_CS_DRV_ODTOFF_SHIFT (8)
225 /* 3:8bank, 2:4bank */
227 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
229 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
251 /* store result of read and write training, for ddr_dq_eye tool in u-boot */
259 u16 dq_deskew[8];
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H A Dsdram.h4 * SPDX-License-Identifier: GPL-2.0+
17 LPDDR4X = 8,
26 u64 para[8];
45 * [8] bk_ch0
63 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
65 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
66 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
68 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
70 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
72 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
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/OK3568_Linux_fs/buildroot/dl/sox/git/src/
H A Dima_rw.c1 /* libSoX ima_rw.c -- codex utilities for WAV_FORMAT_IMA_ADPCM
16 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
34 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19, 21, 23, 25, 28, 31, 34,
44 #define imaStateAdjust(c) (((c)<4)? -1:(2*(c)-6))
45 /* +0 - +3, decrease step size */
46 /* +4 - +7, increase step size */
47 /* -0 - -3, decrease step size */
48 /* -4 - -7, increase step size */
50 static unsigned char imaStateAdjustTable[ISSTMAX+1][8];
56 for (j=0; j<8; j++) { in lsx_ima_init_table()
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H A Dadpcm.c4 * see LACK-OF-WARRANTY information below.
20 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
45 #define lsbshortldi(x,p) { (x)=((short)((int)(p)[0] + ((int)(p)[1]<<8))); (p) += 2; }
51 /* these are step-size adjust factors, where
66 { 512,-256},
70 { 460,-208},
71 { 392,-232}
87 step = state->step; in AdpcmDecode()
90 nstep = (stepAdjustTable[c] * step) >> 8; in AdpcmDecode()
91 state->step = (nstep < 16)? 16:nstep; in AdpcmDecode()
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dsh_mobile_lcdcfb.c16 #include <linux/dma-mapping.h>
36 /* ----------------------------------------------------------------------------
42 #define LDBCR_UPF(n) (1 << ((n) + 8))
66 #define LDBBSIFR_SWPB (1 << 8)
95 #define LDBBSAYR_FG1G_MASK (0xff << 8)
96 #define LDBBSAYR_FG1G_SHIFT 8
104 #define LDBBSACR_FG2G_MASK (0xff << 8)
105 #define LDBBSACR_FG2G_SHIFT 8
113 #define LDBBSAAR_GY_MASK (0xff << 8)
114 #define LDBBSAAR_GY_SHIFT 8
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/OK3568_Linux_fs/kernel/arch/x86/crypto/
H A Dsha512-avx2-asm.S2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
100 XFER_SIZE = 4*8
101 SRND_SIZE = 1*8
102 INP_SIZE = 1*8
103 INPEND_SIZE = 1*8
104 CTX_SIZE = 1*8
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/OK3568_Linux_fs/u-boot/arch/x86/cpu/quark/
H A Dsmc.c8 * SPDX-License-Identifier: Intel
26 350000, /* 8Gb */
88 tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */ in prog_ddr_timing_control()
89 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
92 tras = MCEIL(mrc_params->params.ras, tck); in prog_ddr_timing_control()
94 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in prog_ddr_timing_control()
97 twtr = MCEIL(mrc_params->params.wtr, tck); in prog_ddr_timing_control()
98 trrd = MCEIL(mrc_params->params.rrd, tck); in prog_ddr_timing_control()
100 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
102 wl = 5 + mrc_params->ddr_speed; in prog_ddr_timing_control()
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/OK3568_Linux_fs/kernel/sound/pci/emu10k1/
H A Demu10k1_callback.c1 // SPDX-License-Identifier: GPL-2.0-or-later
42 * macro evaluates its args more than once, so changed to upper-case.
67 emux->ops = emu10k1_ops; in snd_emu10k1_ops_setup()
86 emu = hw->synth; in snd_emu10k1_synth_get_voice()
91 int ch; in snd_emu10k1_synth_get_voice() local
92 vp = &emu->voices[best[i].voice]; in snd_emu10k1_synth_get_voice()
93 if ((ch = vp->ch) < 0) { in snd_emu10k1_synth_get_voice()
95 dev_warn(emu->card->dev, in snd_emu10k1_synth_get_voice()
96 "synth_get_voice: ch < 0 (%d) ??", i); in snd_emu10k1_synth_get_voice()
100 vp->emu->num_voices--; in snd_emu10k1_synth_get_voice()
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/OK3568_Linux_fs/yocto/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Des-Huesca1 # DVB-T Huesca (Aragon) [Spain] [es-Huesca]
3 #------------------------------------------------------------------------------
5 [CH 43 HTV-HuescaTelevision]
12 TRANSMISSION_MODE = 8K
17 [CH 44 La Sexta 2]
24 TRANSMISSION_MODE = 8K
29 [CH 45 TVE HD]
36 TRANSMISSION_MODE = 8K
41 [CH 48 NITRO]
48 TRANSMISSION_MODE = 8K
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/OK3568_Linux_fs/kernel/sound/soc/rockchip/
H A Drockchip_dlp.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Sugar Zhang <sugar.zhang@rock-chips.com>
18 #include <linux/dma-mapping.h>
40 "2CH: 1 Loopback + 1 Mic",
41 "2CH: 1 Mic + 1 Loopback",
42 "2CH: 1 Mic + 1 Loopback-mixed",
43 "2CH: 2 Loopbacks",
44 "4CH: 2 Mics + 2 Loopbacks",
45 "4CH: 2 Mics + 1 Loopback-mixed",
46 "4CH: 4 Loopbacks",
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/
H A Dhci_fc.c29 {8, 3792, grp_0}, /* ACH 4 */
30 {8, 3792, grp_0}, /* ACH 5 */
31 {8, 3792, grp_0}, /* ACH 6 */
32 {8, 3792, grp_0}, /* ACH 7 */
35 {8, 3792, grp_0}, /* B1MGQ */
36 {8, 3792, grp_0}, /* B1HIQ */
45 {8, 3284, grp_0}, /* ACH 4 */
46 {8, 3284, grp_0}, /* ACH 5 */
47 {8, 3284, grp_0}, /* ACH 6 */
48 {8, 3284, grp_0}, /* ACH 7 */
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/
H A Dhci_fc.c29 {8, 3792, grp_0}, /* ACH 4 */
30 {8, 3792, grp_0}, /* ACH 5 */
31 {8, 3792, grp_0}, /* ACH 6 */
32 {8, 3792, grp_0}, /* ACH 7 */
35 {8, 3792, grp_0}, /* B1MGQ */
36 {8, 3792, grp_0}, /* B1HIQ */
45 {8, 3284, grp_0}, /* ACH 4 */
46 {8, 3284, grp_0}, /* ACH 5 */
47 {8, 3284, grp_0}, /* ACH 6 */
48 {8, 3284, grp_0}, /* ACH 7 */
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/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/spirit/home/support/char_encoding/
H A Diso8859_1.hpp2 Copyright (c) 2001-2011 Hartmut Kaiser
3 Copyright (c) 2001-2011 Joel de Guzman
38 // ISO 8859-1 character classification table
40 // the comments intentionally contain non-ascii characters
53 /* BS 8 8 */ BOOST_CC_CTRL,
90 /* - 45 2d */ BOOST_CC_PUNCT,
101 /* 8 56 38 */ BOOST_CC_DIGIT|BOOST_CC_XDIGIT,
173 /* -- 128 80 */ BOOST_CC_CTRL,
174 /* -- 129 81 */ BOOST_CC_CTRL,
175 /* -- 130 82 */ BOOST_CC_CTRL,
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/OK3568_Linux_fs/kernel/drivers/media/pci/solo6x10/
H A Dsolo6x10-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
17 #include "solo6x10-offsets.h"
34 #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8)
53 #define SOLO_VCLK_VIN0809_DELAY(n) ((n)<<8)
70 #define SOLO_IRQ_PS2_0 BIT(8)
107 #define SOLO_P2M_CSC_BYTE_REORDER BIT(5) /* BGR -> RGB */
121 #define SOLO_P2M_COMMAND_DONE BIT(8)
135 /* 0:Y[0]<-0(OFF), 1:Y[0]<-1(ON), 2:Y[0]<-G[0], 3:Y[0]<-Bit[15] */
167 #define SOLO_FI_INV_DISP_LIVE(n) ((n)<<8)
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/OK3568_Linux_fs/kernel/drivers/tty/serial/jsm/
H A Djsm_neo.c1 // SPDX-License-Identifier: GPL-2.0+
20 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
35 static void neo_set_cts_flow_control(struct jsm_channel *ch) in neo_set_cts_flow_control() argument
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
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/OK3568_Linux_fs/u-boot/drivers/video/
H A Dipu_regs.h2 * Porting to u-boot:
9 * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
18 #define IPU_MCU_T_DEFAULT 8
63 #define DC_EVT_NEW_DATA 8
73 #define DC_EVT_NEW_CHAN_R_0 8
79 #define SW_IPU_RST 8
121 DP_COM_CONF_CSC_DEF_OFFSET = 8,
144 DI_SYNC_NONE = -1,
201 u32 gamma_c_async[8];
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