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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/
H A Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
28 - enum:
29 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
30 - ad,ad7414
31 # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
32 - ad,adm9240
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/da9062/
H A Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
159 #define DA9062AA_REVERT_SHIFT 7
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dmax96755f.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <asm-generic/gpio.h>
18 #define DEV_ADDR GENMASK(7, 1)
19 #define CFG_BLOCK BIT(0)
22 #define IIC_2_EN BIT(7)
23 #define IIC_1_EN BIT(6)
24 #define DIS_REM_CC BIT(4)
28 #define VID_TX_EN_U BIT(7)
29 #define VID_TX_EN_Z BIT(6)
30 #define VID_TX_EN_Y BIT(5)
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Dmax96755f.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Defining registers address and its bit definitions of MAX96752F
31 #define DEV_ADDR GENMASK(7, 1)
32 #define CFG_BLOCK BIT(0)
35 #define IIC_2_EN BIT(7)
36 #define IIC_1_EN BIT(6)
37 #define DIS_REM_CC BIT(4)
41 #define VID_TX_EN_U BIT(7)
42 #define VID_TX_EN_Z BIT(6)
43 #define VID_TX_EN_Y BIT(5)
[all …]
H A Dmax96745.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Defining registers address and its bit definitions of MAX96745
29 #define PU_LF3 BIT(3)
30 #define PU_LF2 BIT(2)
31 #define PU_LF1 BIT(1)
32 #define PU_LF0 BIT(0)
35 #define RESET_ALL BIT(7)
36 #define SLEEP BIT(3)
39 #define CXTP_B BIT(2)
40 #define CXTP_A BIT(0)
[all …]
/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg7 # SPDX-License-Identifier: GPL-2.0+
9 # Refer doc/README.kwbimage for more details about how-to configure
12 # This configuration applies to COGE5 design (ARM-part)
13 # Two 8-Bit devices are connected on the 16-Bit bus on the same
14 # chip-select. The supported devices are
15 # MT47H256M8EB-3IT:C
16 # MT47H256M8EB-25EIT:C
22 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
23 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
24 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
H A Dkwbimage_128M16_1.cfg10 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/da9150/
H A Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * DA9150 MFD Driver - Registers
160 #define DA9150_WRITE_MODE_MASK BIT(6)
161 #define DA9150_REVERT_SHIFT 7
162 #define DA9150_REVERT_MASK BIT(7)
172 #define DA9150_VFAULT_STAT_MASK BIT(0)
174 #define DA9150_TFAULT_STAT_MASK BIT(1)
178 #define DA9150_VDD33_STAT_MASK BIT(0)
180 #define DA9150_VDD33_SLEEP_MASK BIT(1)
181 #define DA9150_LFOSC_STAT_SHIFT 7
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/mac_8852b/
H A Dgpio_8852b.c23 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
26 0x4F, BIT(5), BIT(5)}
29 0x66, BIT(6), BIT(6)}
32 0x4F, BIT(6), BIT(6)}
35 0x41, BIT(1), BIT(1)}
38 0x41, BIT(2), BIT(2)}
41 0x40, BIT(1) | BIT(0), BIT(0)}
44 0x40, BIT(1) | BIT(0), BIT(1)}
47 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
50 0x142, BIT(0), BIT(0)}
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/mac_8852b/
H A Dgpio_8852b.c23 0x66, BIT(2) | BIT(1) | BIT(0), BIT(2)}
26 0x4F, BIT(5), BIT(5)}
29 0x66, BIT(6), BIT(6)}
32 0x4F, BIT(6), BIT(6)}
35 0x41, BIT(1), BIT(1)}
38 0x41, BIT(2), BIT(2)}
41 0x40, BIT(1) | BIT(0), BIT(0)}
44 0x40, BIT(1) | BIT(0), BIT(1)}
47 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
50 0x142, BIT(0), BIT(0)}
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
36 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
39 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
40 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
42 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
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/OK3568_Linux_fs/kernel/drivers/net/dsa/microchip/
H A Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
34 #define SW_NEW_BACKOFF BIT(7)
35 #define SW_GLOBAL_RESET BIT(6)
36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
38 #define SW_LINK_AUTO_AGING BIT(0)
42 #define SW_HUGE_PACKET BIT(6)
43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
45 #define SW_CHECK_LENGTH BIT(3)
[all …]
H A Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
[all …]
/OK3568_Linux_fs/kernel/include/linux/soundwire/
H A Dsdw_registers.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
36 #define SDW_DP0_INT_TEST_FAIL BIT(0)
37 #define SDW_DP0_INT_PORT_READY BIT(1)
38 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
39 #define SDW_DP0_SDCA_CASCADE BIT(3)
40 /* BIT(4) not allocated in SoundWire specification 1.2 */
41 #define SDW_DP0_INT_IMPDEF1 BIT(5)
42 #define SDW_DP0_INT_IMPDEF2 BIT(6)
43 #define SDW_DP0_INT_IMPDEF3 BIT(7)
[all …]
/OK3568_Linux_fs/kernel/Documentation/input/devices/
H A Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
25 5.2.1 Parity checking and packet re-synchronization
33 7. Hardware version 4
114 non-zero value will turn it ON. For hardware version 1 the default is ON.
118 calculating a parity bit for the last 3 bytes of each packet. The driver
145 4 bytes version: (after the arrow is the name given in the Dell-provided driver)
173 ---------
179 echo -n 0x16 > reg_10
183 bit 7 6 5 4 3 2 1 0
197 bit 7 6 5 4 3 2 1 0
[all …]
/OK3568_Linux_fs/kernel/sound/soc/hisilicon/
H A Dhi6210-i2s.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/soc/hisilicon/hi6210-i2s.h
29 #define HII2S_SW_RST_N__SW_RST_N BIT(0)
41 #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN BIT(25)
42 #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN BIT(24)
43 #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN BIT(20)
44 #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN BIT(16)
45 #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN BIT(15)
46 #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN BIT(14)
47 #define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN BIT(13)
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A DBusLogic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 Copyright 1995-1998 by Leonard N. Zubkoff <lnz@dandelion.com>
12 Special thanks to Wayne Yen, Jin-Lon Hon, and Alex Win of BusLogic, whose
60 #define BLOGIC_MIN_AUTO_TAG_DEPTH 7
91 #define BLOGIC_CCB_GRP_ALLOCSIZE 7
160 (adapter->adapter_type == BLOGIC_MULTIMASTER)
163 (adapter->adapter_type == BLOGIC_FLASHPOINT)
189 BLOGIC_VESA_BUS, /* BT-4xx */
190 BLOGIC_ISA_BUS, /* BT-5xx */
191 BLOGIC_MCA_BUS, /* BT-6xx */
[all …]
/OK3568_Linux_fs/kernel/sound/soc/rockchip/
H A Drockchip_spdifrx.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ALSA SoC Audio Layer - Rockchip SPDIF_RX Controller driver
15 #define SPDIFRX_CFGR_TWAD_STREAM BIT(1)
16 #define SPDIFRX_EN_MASK BIT(0)
17 #define SPDIFRX_EN BIT(0)
21 #define SPDIFRX_CLR_RXSC BIT(0)
25 #define SPDIFRX_CDR_AVGSEL_MASK BIT(1)
27 #define SPDIFRX_CDR_AVGSEL_AVG BIT(1)
28 #define SPDIFRX_CDR_BYPASS_MASK BIT(0)
29 #define SPDIFRX_CDR_BYPASS_EN BIT(0)
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/wil6210/
H A Dtxrx.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
[all …]
/OK3568_Linux_fs/kernel/drivers/platform/x86/
H A Dmlx-platform.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
12 #include <linux/i2c-mux.h>
16 #include <linux/platform_data/i2c-mux-reg.h>
130 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
132 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6)
140 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
147 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1)
171 #define MLXPLAT_CPLD_NR_NONE -1
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_hdmitx.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Author: Chen Shunqing <csq@rock-chips.com>
29 #define RST_ANALOG_MASK BIT(6)
31 #define RST_DIGITAL_MASK BIT(5)
33 #define REG_CLK_INV_MASK BIT(4)
35 #define VCLK_INV_MASK BIT(3)
37 #define REG_CLK_SOURCE_MASK BIT(2)
39 #define POWER_MASK BIT(1)
41 #define INT_POL_MASK BIT(0)
49 #define DE_SOURCE_MASK BIT(0)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/halmac/halmac_88xx/halmac_8822c/
H A Dhalmac_pwr_seq_8822c.c3 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
26 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
31 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
36 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
41 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
46 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
51 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
56 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
70 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
75 HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dtda1997x_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
125 #define DETECT_UTIL BIT(7) /* utility of HDMI level */
126 #define DETECT_HPD BIT(6) /* HPD of HDMI level */
127 #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
128 #define DETECT_5V_B BIT(1) /* 5V present on input B */
129 #define DETECT_5V_A BIT(0) /* 5V present on input A */
132 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
133 #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
134 #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ieee802154/
H A Dmcr20a.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
50 /*------------------ 0x27 */
69 /*----------------------- 0x3A */
118 /*-------------------- 0x29 */
124 /*------------------ 0x2F */
128 /*------------------- 0x33 */
147 /*-------------------- 0x46 */
163 /*------------------- 0x56 */
164 /*------------------- 0x57 */
[all …]

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