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/OK3568_Linux_fs/kernel/arch/x86/kernel/
H A Dtsc_msr.c22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.c65 debug("Only one refclk at 122.88MHz is not supported." in set_serdes_refclk()
66 " Please set both refclk1 & refclk2 to 122.88MHz" in set_serdes_refclk()
67 " or both not to 122.88MHz.\n"); in set_serdes_refclk()
74 debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz" in set_serdes_refclk()
75 " or 156.25MHz.\n"); in set_serdes_refclk()
82 debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz" in set_serdes_refclk()
83 " or 156.25MHz.\n"); in set_serdes_refclk()
93 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz in set_serdes_refclk()
118 * Refclk1 = 100MHz Refclk2 = 125MHz in set_serdes_refclk()
121 printf("Setting refclk1:100 and refclk2:125\n"); in set_serdes_refclk()
[all …]
H A Didt8t49n222a_serdes_clk.h23 SERDES_REFCLK_100, /* refclk 100Mhz */
24 SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
25 SERDES_REFCLK_125, /* refclk 125Mhz */
26 SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
31 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
43 * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
55 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
64 * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
72 * Refclk1 : 100MHz Refclk2 : 156.25MHz
80 * Refclk1 : 125MHz Refclk2 : 156.25MHz
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_config_defaults.h95 #define DEFAULT_PM_DVFS_PERIOD 100 /* 100ms */
118 #define DEFAULT_JS_SCHEDULING_PERIOD_NS (100000000u) /* 100ms */
126 #define DEFAULT_JS_SOFT_STOP_TICKS (1) /* 100ms-200ms */
129 #define DEFAULT_JS_SOFT_STOP_TICKS_CL (1) /* 100ms-200ms */
176 * Based on 75000ms timeout at nominal 100MHz, as is required for Android - based
177 * on scaling from a 50MHz GPU system.
184 * Based on 2500ms timeout at nominal 100MHz, scaled from a 50MHz GPU system.
190 * Based on 2500ms timeout at 100MHz, scaled from a 50MHz GPU system
196 * Based on 1500ms timeout at 100MHz, scaled from a 50MHz GPU system.
202 * Based on 250ms timeout at 100MHz, scaled from a 50MHz GPU system.
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
[all …]
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3568.c50 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
57 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
61 RK3036_PLL_RATE(400000000, 1, 100, 6, 1, 1, 0),
62 RK3036_PLL_RATE(200000000, 1, 100, 6, 2, 1, 0),
739 rate = 200 * MHz; in rk3568_bus_get_clk()
741 rate = 150 * MHz; in rk3568_bus_get_clk()
743 rate = 100 * MHz; in rk3568_bus_get_clk()
752 rate = 100 * MHz; in rk3568_bus_get_clk()
754 rate = 75 * MHz; in rk3568_bus_get_clk()
756 rate = 50 * MHz; in rk3568_bus_get_clk()
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H A Dclk_rv1106.c33 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
86 rate = 400 * MHz; in rv1106_peri_get_clk()
88 rate = 200 * MHz; in rv1106_peri_get_clk()
90 rate = 100 * MHz; in rv1106_peri_get_clk()
98 rate = 200 * MHz; in rv1106_peri_get_clk()
100 rate = 100 * MHz; in rv1106_peri_get_clk()
102 rate = 50 * MHz; in rv1106_peri_get_clk()
110 rate = 100 * MHz; in rv1106_peri_get_clk()
112 rate = 50 * MHz; in rv1106_peri_get_clk()
120 rate = 300 * MHz; in rv1106_peri_get_clk()
[all …]
H A Dclk_rk3588.c161 rate = 702 * MHz; in rk3588_center_get_clk()
163 rate = 396 * MHz; in rk3588_center_get_clk()
165 rate = 200 * MHz; in rk3588_center_get_clk()
174 rate = 500 * MHz; in rk3588_center_get_clk()
176 rate = 250 * MHz; in rk3588_center_get_clk()
178 rate = 100 * MHz; in rk3588_center_get_clk()
187 rate = 396 * MHz; in rk3588_center_get_clk()
189 rate = 200 * MHz; in rk3588_center_get_clk()
191 rate = 100 * MHz; in rk3588_center_get_clk()
200 rate = 200 * MHz; in rk3588_center_get_clk()
[all …]
/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
94 mode "640x480-100"
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/phydm/
H A Drtchnlplan.c89 100~140" "5180~5240, 5260~5230
92 100~140, 149~165" "5180~5240, 5260~5230
95 100~132, 149~165"
99 100~140, 149~165"
101 5500~5700, 5745~5825" Band1(5150~5250MHz),
102 Band2(5250~5350MHz),
103 Band3(5470~5725MHz),
104 Band4(5725~5850MHz)" US
118 100~116, 136, 140,
122 Band3(except 5600~5650MHz),
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/hal/phydm/
H A Drtchnlplan.c89 100~140" "5180~5240, 5260~5230
92 100~140, 149~165" "5180~5240, 5260~5230
95 100~132, 149~165"
99 100~140, 149~165"
101 5500~5700, 5745~5825" Band1(5150~5250MHz),
102 Band2(5250~5350MHz),
103 Band3(5470~5725MHz),
104 Band4(5725~5850MHz)" US
118 100~116, 136, 140,
122 Band3(except 5600~5650MHz),
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822be/hal/phydm/
H A Drtchnlplan.c90 100~140" "5180~5240, 5260~5230
93 100~140, 149~165" "5180~5240, 5260~5230
96 100~132, 149~165"
100 100~140, 149~165"
102 5500~5700, 5745~5825" Band1(5150~5250MHz),
103 Band2(5250~5350MHz),
104 Band3(5470~5725MHz),
105 Band4(5725~5850MHz)" US
119 100~116, 136, 140,
123 Band3(except 5600~5650MHz),
[all …]
/OK3568_Linux_fs/u-boot/board/samsung/odroid/
H A Dodroid.c119 /* Set APLL to 1000MHz */ in board_clock_init()
142 * Set dividers for MOUTcore = 1000 MHz in board_clock_init()
143 * coreout = MOUT / (ratio + 1) = 1000 MHz (0) in board_clock_init()
144 * corem0 = armclk / (ratio + 1) = 333 MHz (2) in board_clock_init()
145 * corem1 = armclk / (ratio + 1) = 166 MHz (5) in board_clock_init()
146 * periph = armclk / (ratio + 1) = 1000 MHz (0) in board_clock_init()
147 * atbout = MOUT / (ratio + 1) = 200 MHz (4) in board_clock_init()
148 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) in board_clock_init()
149 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) in board_clock_init()
150 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) in board_clock_init()
[all …]
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-power.json10 …quency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can al…
14 "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.",
20 …quency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can al…
24 "MetricExpr": "(UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100.",
30 …quency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can al…
34 "MetricExpr": "(UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100.",
40 …quency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can al…
44 "MetricExpr": "(UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100.",
50 …quency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can al…
55 "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.",
[all …]
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/x86/jaketown/
H A Duncore-power.json10 …equency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can al…
14 "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.",
20 …equency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can al…
24 "MetricExpr": "(UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100.",
30 …equency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can al…
34 "MetricExpr": "(UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100.",
40 …quency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can al…
44 "MetricExpr": "(UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100.",
50 …equency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can al…
55 "MetricExpr": "(UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.",
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h78 #define MHz 1000000 macro
80 #define OSC_HZ (24*MHz)
81 #define APLL_HZ (600*MHz)
82 #define GPLL_HZ (800 * MHz)
83 #define CPLL_HZ (384*MHz)
84 #define NPLL_HZ (600 * MHz)
85 #define PPLL_HZ (676*MHz)
87 #define PMU_PCLK_HZ (48*MHz)
89 #define ACLKM_CORE_HZ (300*MHz)
90 #define ATCLK_CORE_HZ (300*MHz)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/et8ek8/
H A Det8ek8_mode.c20 * SPCK = 80 MHz
21 * CCP2 = 640 MHz
22 * VCO = 640 MHz
49 .numerator = 100,
121 * SPCK = 80 MHz
122 * CCP2 = 560 MHz
123 * VCO = 560 MHz
150 .numerator = 100,
177 * SPCK = 96.5333333333333 MHz
178 * CCP2 = 579.2 MHz
[all …]
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
89 #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
91 /* Use 800MHz when entering sleep mode */
129 {0, L4, 100*1000},
175 /* L0 : [1000/200/100][166/83][133/66][200/200] */
178 /* L1 : [800/200/100][166/83][133/66][200/200] */
181 /* L2 : [400/200/100][166/83][133/66][200/200] */
184 /* L3 : [200/200/100][166/83][133/66][200/200] */
187 /* L4 : [100/100/100][83/83][66/66][100/100] */
275 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 in s5pv210_target()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c61 { /* 19.2 MHz */
64 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
69 { /* 24 MHz */
72 {25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
74 {100, 3, 1, -1, -1, -1, -1}, /* OPP TB */
77 { /* 25 MHz */
80 {24, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
85 { /* 26 MHz */
88 {300, 12, 1, -1, -1, -1, -1}, /* OPP 100 */
96 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
[all …]
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dbcmstb_sdhci.c15 * capability is 100 MHz. The divisor that is eventually written to
19 * This define used to be set to 52000000 (52 MHz), the desired
21 * actually running at 100 MHz (seemingly without issue), which is
24 * Now, by setting this to 0 (auto-detect), 100 MHz will be read from
27 * in-spec 52 MHz value.
32 * sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
/OK3568_Linux_fs/u-boot/board/freescale/t102xqds/
H A DREADME100 - Two on-board RGMII 10M/100M/1G ethernet ports.
114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
115 - Software programmable in 1 MHz increments from 1-200 MHz.
118 - 100 MHz, 125 MHz and 156.25 MHz options.
119 - Spread-spectrum option for 100 MHz.
196 0x6F 100MHz 125MHz 1101
197 0xD6 100MHz 100MHz 1111
198 0x99 156.25MHz 100MHz 1011
204 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
205 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
[all …]
/OK3568_Linux_fs/kernel/tools/testing/selftests/intel_pstate/
H A Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
60 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
80 # MAIN (ALL UNITS IN MHZ)
95 [ $EVALUATE_ONLY -eq 0 ] && for freq in `seq $max_freq -100 $min_freq`
98 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
102 [ $EVALUATE_ONLY -eq 0 ] && cpupower frequency-set -g powersave --max=${max_freq}MHz >& /dev/null
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/exynos/
H A Dexynos_mipi_dsi_common.c18 #define MHZ (1000 * 1000) macro
19 #define FIN_HZ (24 * MHZ)
21 #define DFIN_PLL_MIN_HZ (6 * MHZ)
22 #define DFIN_PLL_MAX_HZ (12 * MHZ)
24 #define DFVCO_MIN_HZ (500 * MHZ)
25 #define DFVCO_MAX_HZ (1000 * MHZ)
47 100, 120, 170, 220, 270,
110 delay_val = MHZ / dsim->dsim_config->esc_clk; in exynos_mipi_dsi_wr_data()
268 * ~ 99.99 MHz 0000 in exynos_mipi_dsi_change_pll()
269 * 100 ~ 119.99 MHz 0001 in exynos_mipi_dsi_change_pll()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/spear/
H A Dspear1340_clock.c167 /* PCLK 24MHz */
168 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
170 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
172 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
173 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
180 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
181 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3308.c115 /* DPLL VPLL0 VPLL1 mode in 24MHz*/ in rkdclk_init()
131 /* set vpll1 in 903.168MHz vco = 1.806GHz */ in rkdclk_init()
141 /* set vpll0 in 786.432MHz vco = 3.146GHz */ in rkdclk_init()
149 /* set vpll0 in 1179.648MHz, vco = 2.359GHz*/ in rkdclk_init()
183 /* dpll default set in 1300MHz */ in rkdclk_init()
185 /* set dpll in 1584 MHz ,vco=3.168G*/ in rkdclk_init()
210 /* set aclk_bus 216.7MHz */ in rkdclk_init()
215 /* set pclk_bus 50MHz,hclk_bus 92.857MHz */ in rkdclk_init()
220 /* set crypto 92.857MHz,crypto_apk 92.857MHz */ in rkdclk_init()
228 /* set aclk_peri 216.7MHz */ in rkdclk_init()
[all …]

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