Searched +full:1 +full:- +full:sdxc (Results 1 – 18 of 18) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"10 - Adrian Hunter <adrian.hunter@intel.com>13 - $ref: "mmc-controller.yaml#"14 - if:18 const: arasan,sdhci-5.121 - phys22 - phy-names23 - if:[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>16 #include <asm/mach-ralink/ralink_regs.h>17 #include <asm/mach-ralink/mt7620.h>18 #include <asm/mach-ralink/pinmux.h>53 static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };64 static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };76 FUNC("wdt rst", 0, 17, 1),77 FUNC("wdt refclk", 0, 17, 1),80 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),[all …]
2 ------------------4 combines two or one 64-bit Power Architecture e5500 core respectively with high9 and general-purpose embedded computing. Its high level of integration offers14 - two e5500 cores, each with a private 256 KB L2 cache15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)16 - Three levels of instructions: User, supervisor, and hypervisor17 - Independent boot and reset18 - Secure boot capability19 - 256 KB shared L3 CoreNet platform cache (CPC)20 - Interconnect CoreNet platform[all …]
4 * SPDX-License-Identifier: GPL-2.0+31 struct cpu_type *cpu = gd->arch.cpu; in checkboard()36 printf("Board: %sQDS, ", cpu->name); in checkboard()38 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); in checkboard()80 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); in select_i2c_ch_pca9547()95 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in board_mux_lane_to_slot()149 return -1; in board_mux_lane_to_slot()181 if (hwconfig_arg_cmp("adaptor", "sdxc")) in board_mux_setup()194 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); in board_retimer_ds125df111_init()196 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); in board_retimer_ds125df111_init()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */5 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.26 #define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */33 #define SD_OCR_S18R (1 << 24) /* 1.8V switching request */35 #define SD_OCR_XPC (1 << 28) /* SDXC power control */36 #define SD_OCR_CCS (1 << 30) /* Card Capacity Status */41 * [31] Check (0) or switch (1)48 * [3:0] Function group 163 #define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */64 #define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */[all …]
1 The T2080QDS is a high-performance computing evaluation, development and5 ------------------6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power7 Architecture processor cores with high-performance datapath acceleration12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)14 - Hierarchical interconnect fabric15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration17 - 16 SerDes lanes up to 10.3125 GHz[all …]
2 --------9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).16 The board is re-designed T1040RDB board with following changes :17 - Support of DDR4 memory and some enhancements20 The board is re-designed T1040RDB board with following changes :21 - Support of DDR4 memory22 - Support for 0x86 serdes protocol which can support following interfaces23 - 2 RGMII's on DTSEC4, DTSEC524 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC327 -------------------------------------------------------------------------[all …]
2 --------6 ------------------8 is built on Layerscape architecture, the industry's first software-aware,9 core-agnostic networking architecture to offer unprecedented efficiency12 A member of the value-performance tier, the QorIQ LS1021A processor provides14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark17 security features and the broadest array of high-speed interconnects and18 optimized peripheral features ever offered in a sub-3 W processor.23 protection on both L1 and L2 caches. The LS1021A processor is pin- and[all …]
1 // SPDX-License-Identifier: GPL-2.07 #include <linux/clk-provider.h>10 #include <dt-bindings/clock/intel,lgm-clk.h>11 #include "clk-cgu.h"29 #define G_LEDC0_SHIFT 160 #define G_PCIE10_SHIFT 1115 #define CLK_NR_CLKS (LGM_GCLK_USB2 + 1)119 * It's more efficient to provide an explicit table due to non-linear123 { .val = 0, .div = 1 },124 { .val = 1, .div = 2 },[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */15 #define mmc_card_name(c) ((c)->cid.prod_name)16 #define mmc_card_id(c) (dev_name(&(c)->dev))20 #define MMC_STATE_PRESENT (1<<0) /* present in sysfs */21 #define MMC_STATE_READONLY (1<<1) /* card is read-only */22 #define MMC_STATE_BLOCKADDR (1<<2) /* card uses block-addressing */23 #define MMC_CARD_SDXC (1<<3) /* card is SDXC */24 #define MMC_CARD_REMOVED (1<<4) /* card has been removed */25 #define MMC_STATE_SUSPENDED (1<<5) /* card is suspended */27 #define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT)[all …]
1 // SPDX-License-Identifier: GPL-2.0-only35 switch (card->type) { in type_show()45 return -EFAULT; in type_show()57 * This currently matches any MMC driver to any MMC card - drivers63 return 1; in mmc_bus_match()74 switch (card->type) { in mmc_bus_uevent()97 if (card->type == MMC_TYPE_SDIO || card->type == MMC_TYPE_SD_COMBO) { in mmc_bus_uevent()99 card->cis.vendor, card->cis.device); in mmc_bus_uevent()104 card->major_rev, card->minor_rev); in mmc_bus_uevent()108 for (i = 0; i < card->num_info; i++) { in mmc_bus_uevent()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only5 * Copyright (C) 2003-2004 Russell King, All Rights Reserved.7 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.42 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,60 const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \61 const int __off = 3 - ((start) / 32); \67 __res |= resp[__off-1] << ((32 - __shft) % 32); \76 u32 *resp = card->raw_cid; in mmc_decode_cid()82 card->cid.manfid = UNSTUFF_BITS(resp, 120, 8); in mmc_decode_cid()83 card->cid.oemid = UNSTUFF_BITS(resp, 104, 16); in mmc_decode_cid()[all …]
1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.5 ------------------6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power7 Architecture processor cores with high-performance datapath acceleration12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)14 - Hierarchical interconnect fabric15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration17 - 16 SerDes lanes up to 10.3125 GHz[all …]
1 // SPDX-License-Identifier: GPL-2.0 OR MIT7 #include <dt-bindings/clock/meson8-ddr-clkc.h>8 #include <dt-bindings/clock/meson8b-clkc.h>9 #include <dt-bindings/gpio/meson8b-gpio.h>10 #include <dt-bindings/power/meson8-power.h>11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>17 #address-cells = <1>;18 #size-cells = <0>;22 compatible = "arm,cortex-a5";[all …]
1 // SPDX-License-Identifier: GPL-2.0 OR MIT6 #include <dt-bindings/clock/meson8-ddr-clkc.h>7 #include <dt-bindings/clock/meson8b-clkc.h>8 #include <dt-bindings/gpio/meson8-gpio.h>9 #include <dt-bindings/power/meson8-power.h>10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>19 #address-cells = <1>;20 #size-cells = <0>;24 compatible = "arm,cortex-a9";[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>9 * Based on sdhci-of-esdhc.c18 #include <linux/clk-provider.h>25 #include <linux/firmware/xlnx-zynqmp.h>28 #include "sdhci-cqhci.h"29 #include "sdhci-pltfm.h"56 * On some SoCs the syscon area has a feature where the upper 16-bits of57 * each 32-bit register act as a write mask for the lower 16-bits. This allows65 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map[all …]
... ]; then 78 /usr/lib/command-not-found -- "$1" 79 return $ ...