Home
last modified time | relevance | path

Searched +full:1 +full:- +full:bit (Results 1 – 25 of 1236) sorted by relevance

12345678910>>...50

/OK3568_Linux_fs/kernel/drivers/net/ethernet/freescale/dpaa2/
H A Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
25 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
32 DPKG_FROM_FIELD = 1,
37 * enum dpkg_extract_type - Enumeration for selecting extraction type
40 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
46 DPKG_EXTRACT_FROM_DATA = 1,
51 * struct dpkg_mask - A structure for defining a single extraction mask
63 #define NH_FLD_ETH_DA BIT(0)
64 #define NH_FLD_ETH_SA BIT(1)
[all …]
/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg7 # SPDX-License-Identifier: GPL-2.0+
9 # Refer doc/README.kwbimage for more details about how-to configure
12 # This configuration applies to COGE5 design (ARM-part)
13 # Two 8-Bit devices are connected on the 16-Bit bus on the same
14 # chip-select. The supported devices are
15 # MT47H256M8EB-3IT:C
16 # MT47H256M8EB-25EIT:C
22 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
23 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
24 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
H A Dkwbimage_128M16_1.cfg10 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
[all …]
/OK3568_Linux_fs/kernel/drivers/net/fddi/skfp/h/
H A Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/halmac/halmac_88xx/halmac_8822c/
H A Dhalmac_gpio_8822c.c3 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
23 0x66, BIT(2), BIT(2)}
26 0x4F, BIT(5), BIT(5)}
29 0x66, BIT(6), BIT(6)}
32 0x4F, BIT(6), BIT(6)}
35 0x41, BIT(1), 0}
38 0x41, BIT(2), BIT(2)}
41 0x40, BIT(1) | BIT(0), BIT(0)}
44 0x40, BIT(1) | BIT(0), BIT(1)}
47 0x40, BIT(1) | BIT(0), BIT(1) | BIT(0)}
[all …]
/OK3568_Linux_fs/kernel/drivers/net/dsa/microchip/
H A Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
[all …]
H A Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 #define SW_REVISION_S 1
34 #define SW_NEW_BACKOFF BIT(7)
35 #define SW_GLOBAL_RESET BIT(6)
36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
38 #define SW_LINK_AUTO_AGING BIT(0)
42 #define SW_HUGE_PACKET BIT(6)
43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
16 #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
137 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
[all …]
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/hal/halmac/halmac_88xx/halmac_8821c/
H A Dhalmac_gpio_8821c.c1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
25 0x66, BIT(2), BIT(2)}
28 0x66, BIT(2), BIT(2)}
31 0x41, BIT(1), 0}
34 0x41, BIT(2), BIT(2)}
37 0x40, BIT(1) | BIT(0), BIT(0)}
40 0x40, BIT(1) | BIT(0), BIT(1)}
43 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
46 0x40, BIT(1) | BIT(0), 0}
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/hal/halmac/halmac_88xx/halmac_8821c/
H A Dhalmac_gpio_8821c.c3 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
24 0x66, BIT(2), BIT(2)}
27 0x66, BIT(2), BIT(2)}
30 0x41, BIT(1), 0}
33 0x41, BIT(2), BIT(2)}
36 0x40, BIT(1) | BIT(0), BIT(0)}
39 0x40, BIT(1) | BIT(0), BIT(1)}
42 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
45 0x40, BIT(1) | BIT(0), 0}
50 0x66, BIT(2), BIT(2)}
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/hal/halmac/halmac_88xx/halmac_8822b/
H A Dhalmac_gpio_8822b.c3 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
24 0x66, BIT(2), BIT(2)}
27 0x41, BIT(1), 0}
30 0x41, BIT(2), BIT(2)}
33 0x40, BIT(1) | BIT(0), BIT(0)}
36 0x40, BIT(1) | BIT(0), BIT(1)}
39 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
42 0x40, BIT(1) | BIT(0), 0}
47 0x66, BIT(2), BIT(2)}
50 0x66, BIT(2), BIT(2)}
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/wil6210/
H A Dtxrx.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
13 #define BUF_SW_OWNED (1)
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
[all …]
H A Dtxrx_edma.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved.
22 #define WIL_TX_STATUS_IRQ_IDX 1
28 #define WIL_EDMA_TIME_UNIT_CLK_CYCLES (330) /* fits 1 usec */
31 #define WIL_RX_EDMA_ERROR_MIC (1)
37 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
38 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
40 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11)
49 #define WIL_RX_EDMA_MID_VALID_BIT BIT(20)
55 #define WIL_EDMA_DESC_TX_CFG_EOP_LEN 1
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rcar-du/
H A Drcar_du_drv.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_drv.c -- R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
32 /* -----------------------------------------------------------------------------
41 .channels_mask = BIT(1) | BIT(0),
47 .possible_crtcs = BIT(1) | BIT(0),
51 .possible_crtcs = BIT(0),
52 .port = 1,
55 .num_lvds = 1,
63 .channels_mask = BIT(1) | BIT(0),
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/cortina/
H A Dgemini.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
57 #define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
91 /* GMAC 0/1 DMA/TOE register */
148 /* TOE GMAC 0/1 register */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
19 * Default 1.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
[all …]
/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
44 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
H A Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
40 * terminal count" bit, and a data transfer direction.
50 * Register Offsets and Bit Definitions
55 /* Local Address Space 1 Range Register */
58 #define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
59 #define PLX_LASRR_MLOC_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/phydm/halrf/
H A Dhalrf_kfree.c3 * Copyright(c) 2007 - 2017 Realtek Corporation.
34 struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm->rf_calibrate_info); in phydm_set_kfree_to_rf_8814a()
37 if ((data % 2) != 0) { /*odd->positive*/ in phydm_set_kfree_to_rf_8814a()
38 data = data - 1; in phydm_set_kfree_to_rf_8814a()
39 odm_set_rf_reg(p_dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1); in phydm_set_kfree_to_rf_8814a()
41 } else { /*even->negative*/ in phydm_set_kfree_to_rf_8814a()
42 odm_set_rf_reg(p_dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0); in phydm_set_kfree_to_rf_8814a()
48 odm_set_rf_reg(p_dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); in phydm_set_kfree_to_rf_8814a()
49 odm_set_rf_reg(p_dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0); in phydm_set_kfree_to_rf_8814a()
50 p_rf_calibrate_info->kfree_offset[e_rf_path] = 0; in phydm_set_kfree_to_rf_8814a()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/
H A Di915_pci.c39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
161 .is_mobile = 1, \
162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
163 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
164 .display.has_overlay = 1, \
165 .display.cursor_needs_physical = 1, \
166 .display.overlay_needs_physical = 1, \
167 .display.has_gmch = 1, \
169 .hws_needs_physical = 1, \
170 .unfenced_needs_alignment = 1, \
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Drk_codec_digital.h1 /* SPDX-License-Identifier: GPL-2.0 */
75 #define ACDCDIG_SYSCTRL0_SYNC_SEL_MASK BIT(1)
76 #define ACDCDIG_SYSCTRL0_SYNC_SEL_DAC BIT(1)
78 #define ACDCDIG_SYSCTRL0_GLB_CKE_MASK BIT(3)
79 #define ACDCDIG_SYSCTRL0_GLB_CKE_EN BIT(3)
81 #define ACDCDIG_SYSCTRL0_CLK_COM_SEL_MASK BIT(4)
82 #define ACDCDIG_SYSCTRL0_CLK_COM_SEL_DAC BIT(4)
84 #define ACDCDIG_SYSCTRL0_SYNC_MODE_MASK BIT(5)
85 #define ACDCDIG_SYSCTRL0_SYNC_MODE_SYNC BIT(5)
88 #define ACDCDIG_ADCVUCTL_ADC_BYPS_MASK BIT(2)
[all …]
/OK3568_Linux_fs/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3308.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "pinctrl-rockchip.h"
20 .func = 1,
22 .route_val = BIT(16 + 0) | BIT(0),
25 .bank_num = 1,
29 .route_val = BIT(16 + 2) | BIT(16 + 3),
36 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
43 .route_val = BIT(16 + 4),
50 .route_val = BIT(16 + 4) | BIT(4),
52 /* i2s-8ch-1-sclktxm0 */
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNRGAMA 64G 3.3V 8-bit",
50 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
[all …]

12345678910>>...50