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/OK3568_Linux_fs/kernel/drivers/firmware/broadcom/
H A Dbcm47xx_sprom.c76 if (err < 0) \
78 err = kstrto ## type(strim(buf), 0, &var); \
104 if (err < 0) in NVRAM_READ_VAL()
106 err = kstrtou32(strim(buf), 0, &val); in NVRAM_READ_VAL()
112 *val_lo = (val & 0x0000FFFFU); in NVRAM_READ_VAL()
113 *val_hi = (val & 0xFFFF0000U) >> 16; in NVRAM_READ_VAL()
125 if (err < 0) in nvram_read_leddc()
127 err = kstrtou32(strim(buf), 0, &val); in nvram_read_leddc()
134 if (val == 0xffff || val == 0xffffffff) in nvram_read_leddc()
137 *leddc_on_time = val & 0xff; in nvram_read_leddc()
[all …]
/OK3568_Linux_fs/kernel/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/OK3568_Linux_fs/kernel/include/linux/platform_data/x86/
H A Dpmc_atom.h13 #define PCI_DEVICE_ID_VLV_PMC 0x0F1C
15 #define PCI_DEVICE_ID_CHT_PMC 0x229C
18 #define PMC_BASE_ADDR_OFFSET 0x44
19 #define PMC_BASE_ADDR_MASK 0xFFFFFE00
20 #define PMC_MMIO_REG_LEN 0x100
24 #define PMC_FUNC_DIS 0x34
25 #define PMC_FUNC_DIS_2 0x38
32 #define PMC_S0IX_WAKE_EN 0x3C
47 #define PMC_S0IR_TMR 0x80
48 #define PMC_S0I1_TMR 0x84
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dzynq-common.h22 # define CONFIG_SYS_PL310_BASE 0xf8f02000
25 #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
28 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
62 # define CONFIG_SYS_FLASH_BASE 0xE2000000
89 # define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
97 "${kernel_image} ram 0x3000000 0x500000\\\\;" \
98 "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
99 "${ramdisk_image} ram 0x2000000 0x600000\0" \
100 "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
101 "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rtc/
H A Datmel,at91rm9200-rtc.yaml45 reg = <0xfffffe00 0x100>;
/OK3568_Linux_fs/u-boot/drivers/pch/
H A Dpch9.c11 #define GPIO_BASE 0x48
12 #define IO_BASE 0x4c
13 #define SBASE_ADDR 0x54
20 *sbasep = sbase_addr & 0xfffffe00; in pch9_get_spi_base()
22 return 0; in pch9_get_spi_base()
35 * GPIO base address register bit0 is reserved (read returns 0), in pch9_get_gpio_base()
40 if (base == 0x00000000 || base == 0xffffffff) { in pch9_get_gpio_base()
48 * at the offset that we just read. Bit 0 indicates that it's in pch9_get_gpio_base()
53 return 0; in pch9_get_gpio_base()
61 if (base == 0x00000000 || base == 0xffffffff) { in pch9_get_io_base()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91rm9200.h20 #define ATMEL_ID_USART0 6 /* USART 0 */
28 #define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */
31 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */
47 #define ATMEL_USB_HOST_BASE 0x00300000
49 #define ATMEL_BASE_TC 0xFFFA0000
50 #define ATMEL_BASE_UDP 0xFFFB0000
51 #define ATMEL_BASE_MCI 0xFFFB4000
52 #define ATMEL_BASE_TWI 0xFFFB8000
53 #define ATMEL_BASE_EMAC 0xFFFBC000
54 #define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */
[all …]
H A Dat91sam9rl.h25 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
31 #define ATMEL_ID_USART0 6 /* USART 0 */
36 #define ATMEL_ID_TWI0 11 /* TWI 0 */
39 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
41 #define ATMEL_ID_TC0 16 /* Timer Counter 0 */
55 #define ATMEL_BASE_TCB0 0xfffa0000
56 #define ATMEL_BASE_TC0 0xfffa0000
57 #define ATMEL_BASE_TC1 0xfffa0040
58 #define ATMEL_BASE_TC2 0xfffa0080
59 #define ATMEL_BASE_MCI 0xfffa4000
[all …]
H A Dat91sam9x5.h20 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
26 #define ATMEL_ID_USART0 5 /* USART 0 */
30 #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
33 #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
34 #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
36 #define ATMEL_ID_UART0 15 /* UART 0 */
38 #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
41 #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
56 #define ATMEL_BASE_SPI0 0xf0000000
57 #define ATMEL_BASE_SPI1 0xf0004000
[all …]
H A Dsama5d3.h24 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
36 #define ATMEL_ID_USART0 12 /* USART 0 */
42 #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
45 #define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
48 #define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
62 #define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
76 #define ARCH_ID_SAMA5D3 0x8a5c07c0
77 #define ARCH_EXID_SAMA5D31 0x00444300
78 #define ARCH_EXID_SAMA5D33 0x00414300
79 #define ARCH_EXID_SAMA5D34 0x00414301
[all …]
/OK3568_Linux_fs/kernel/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/nohash/32/
H A Dmmu-8xx.h16 #define MI_GPM 0x80000000 /* Set domain manager mode */
17 #define MI_PPM 0x40000000 /* Set subpage protection */
18 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
19 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
20 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
21 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
24 * Ks = 0, Kp = 1.
27 #define MI_Ks 0x80000000 /* Should not be set */
28 #define MI_Kp 0x40000000 /* Should always be set */
39 * 0 => Kernel => 11 (all accesses performed according as user iaw page definition)
[all …]
/OK3568_Linux_fs/kernel/drivers/char/
H A Dds1620.c26 #define THERM_START_CONVERT 0xee
27 #define THERM_RESET 0xaf
28 #define THERM_READ_CONFIG 0xac
29 #define THERM_READ_TEMP 0xaa
30 #define THERM_READ_TL 0xa2
31 #define THERM_READ_TH 0xa1
32 #define THERM_WRITE_CONFIG 0x0c
33 #define THERM_WRITE_TL 0x02
34 #define THERM_WRITE_TH 0x01
53 nw_gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0); in netwinder_ds1620_set_clk()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_set_pwr_table_8852b.c22 s16 total = 0; in _halrf_avg_power_8852b()
26 for (i = 0; i < n; i++) { in _halrf_avg_power_8852b()
42 for (k = 0; k < n; k++) in _halrf_bub_sort_8852b()
45 for (i = n - 1; i >= 0; i--) { in _halrf_bub_sort_8852b()
47 for (j = 0; j < i; j++) { in _halrf_bub_sort_8852b()
52 sp = 0; in _halrf_bub_sort_8852b()
59 for (k = 0; k < n; k++) in _halrf_bub_sort_8852b()
71 …rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK1, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
72 …rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK2, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
73 …rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK5_5, 0, 0… in halrf_set_power_by_rate_to_struct_8852b()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_set_pwr_table_8852b.c22 s16 total = 0; in _halrf_avg_power_8852b()
26 for (i = 0; i < n; i++) { in _halrf_avg_power_8852b()
42 for (k = 0; k < n; k++) in _halrf_bub_sort_8852b()
45 for (i = n - 1; i >= 0; i--) { in _halrf_bub_sort_8852b()
47 for (j = 0; j < i; j++) { in _halrf_bub_sort_8852b()
52 sp = 0; in _halrf_bub_sort_8852b()
59 for (k = 0; k < n; k++) in _halrf_bub_sort_8852b()
71 …rate->pwr_by_rate_lgcy[0] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK1, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
72 …rate->pwr_by_rate_lgcy[1] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK2, 0, 0) … in halrf_set_power_by_rate_to_struct_8852b()
73 …rate->pwr_by_rate_lgcy[2] = halrf_get_power_by_rate(rf, phy, RF_PATH_A, RTW_DATA_RATE_CCK5_5, 0, 0… in halrf_set_power_by_rate_to_struct_8852b()
[all …]
/OK3568_Linux_fs/u-boot/tools/binman/
H A Dfunc_test.py34 ME_DATA = '0abcd'
58 # Handle the case where argv[0] is 'python'
59 self._binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
123 Return value (0 for success)
192 self.assertEqual(0, retcode)
207 return self._DoReadFileDtb(fname, use_real_dtb)[0]
249 pos = 0
263 return struct.unpack('>L', dtb[4:8])[0]
274 self.assertEqual(0, len(result.stderr))
275 self.assertEqual(0, result.return_code)
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/controller/
H A Dpci-thunder-pem.c20 #define PEM_CFG_WR 0x28
21 #define PEM_CFG_RD 0x30
35 if (devfn != 0 || where >= 2048) { in thunder_pem_bridge_read()
36 *val = ~0; in thunder_pem_bridge_read()
55 case 0x40: in thunder_pem_bridge_read()
56 read_val &= 0xffff00ff; in thunder_pem_bridge_read()
57 read_val |= 0x00007000; /* Skip MSI CAP */ in thunder_pem_bridge_read()
59 case 0x70: /* Express Cap */ in thunder_pem_bridge_read()
62 * reads as 0, else leave it alone. in thunder_pem_bridge_read()
64 if (!(read_val & (0x1f << 25))) in thunder_pem_bridge_read()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/ssv6xxx/include/
H A Dssv6200_aux.h17 #define MCU_ENABLE_MSK 0x00000001
18 #define MCU_ENABLE_I_MSK 0xfffffffe
19 #define MCU_ENABLE_SFT 0
20 #define MCU_ENABLE_HI 0
22 #define MAC_SW_RST_MSK 0x00000002
23 #define MAC_SW_RST_I_MSK 0xfffffffd
27 #define MCU_SW_RST_MSK 0x00000004
28 #define MCU_SW_RST_I_MSK 0xfffffffb
32 #define SDIO_SW_RST_MSK 0x00000008
33 #define SDIO_SW_RST_I_MSK 0xfffffff7
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2_llh_internal.h12 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR 0x000054C8
13 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK 0x00001000
14 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSKN 0xFFFFEFFF
17 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_DEFAULT 0x0
21 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR 0x000054C8
22 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK 0x000001FF
23 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSKN 0xFFFFFE00
24 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT 0
33 #define HW_ATL2_RPF_NEW_EN_ADR 0x00005104
35 #define HW_ATL2_RPF_NEW_EN_MSK 0x00000800
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/
H A Dat91_emac.c32 #define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
49 #define DEBUG_AT91EMAC 0
55 #define DEBUG_AT91PHY 0
61 #define VERBOSEP 0
64 #define RBF_ADDR 0xfffffffc
65 #define RBF_OWNER (1<<0)
72 #define RBF_SIZE 0x07ff
79 #define RBF_FRAMELEN 0x600
125 return 0; in at91emac_read()
149 return 0; in at91emac_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dvt8500lcdfb.c51 info->var.red.offset = 0; in vt8500lcd_set_par()
53 info->var.red.msb_right = 0; in vt8500lcd_set_par()
55 info->var.green.offset = 0; in vt8500lcd_set_par()
57 info->var.green.msb_right = 0; in vt8500lcd_set_par()
59 info->var.blue.offset = 0; in vt8500lcd_set_par()
61 info->var.blue.msb_right = 0; in vt8500lcd_set_par()
63 info->var.transp.offset = 0; in vt8500lcd_set_par()
64 info->var.transp.length = 0; in vt8500lcd_set_par()
65 info->var.transp.msb_right = 0; in vt8500lcd_set_par()
72 info->var.transp.offset = 0; in vt8500lcd_set_par()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c59 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
63 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
68 u16 bMode, fracMode, aModeRefSel = 0; in ar9002_hw_set_channel()
69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel()
77 reg32 &= 0xc0000000; in ar9002_hw_set_channel()
81 int regWrites = 0; in ar9002_hw_set_channel()
85 aModeRefSel = 0; in ar9002_hw_set_channel()
109 bMode = 0; in ar9002_hw_set_channel()
110 fracMode = 0; in ar9002_hw_set_channel()
113 case 0: in ar9002_hw_set_channel()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Drs690d.h32 #define R_00001E_K8_FB_LOCATION 0x00001E
33 #define R_00005F_MC_MISC_UMA_CNTL 0x00005F
34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
35 #define R_000078_MC_INDEX 0x000078
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF)
38 #define C_000078_MC_IND_ADDR 0xFFFFFE00
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1)
41 #define C_000078_MC_IND_WR_EN 0xFFFFFDFF
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dmmu.h36 /* Values for PP (assumes Ks=0, Kp=1) */
37 #define PP_RWXX 0 /* Supervisor read/write, User none */
45 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
59 unsigned long ks:1; /* Supervisor key (normally 0) */
123 #define PD_MASK 0x02FF
125 #define PT_MASK 0x02FF
144 IBAT0 = 0, IBAT1, IBAT2, IBAT3,
158 #define BATU_VS 0x00000002
159 #define BATU_VP 0x00000001
160 #define BATU_INVALID 0x00000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dat91rm9200.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
54 reg = <0x20000000 0x04000000>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
73 reg = <0x00200000 0x4000>;
76 ranges = <0 0x00200000 0x4000>;
[all …]

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