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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Drockchip,px30-dsi-dphy.yaml14 const: 0
62 reg = <0xff2e0000 0x10000>;
67 #phy-cells = <0>;
H A Dphy-rockchip-inno-video-combo-phy.txt10 - #phy-cells : must be 0. See ./phy-bindings.txt for details.
15 - #clock-cells : from common clock binding; shall be set to 0.
24 reg = <0x0 0xff2e0000 0x0 0x10000>,
25 <0x0 0xff450000 0x0 0x10000>;
29 #clock-cells = <0>;
33 #phy-cells = <0>;
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/px30/
H A Dpx30.c20 #define PMU_PWRDN_CON 0xff000018
21 #define GRF_CPU_CON1 0xff140504
23 #define USBPHY_GRF_BASE 0xff2c0000
24 #define VIDEO_PHY_BASE 0xff2e0000
25 #define FW_DDR_CON_REG 0xff534040
26 #define SERVICE_CORE_ADDR 0xff508000
27 #define QOS_PRIORITY 0x08
36 .virt = 0x0UL,
37 .phys = 0x0UL,
38 .size = 0xff000000UL,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3528/
H A Drk3528.c16 #define FIREWALL_DDR_BASE 0xff2e0000
17 #define FW_DDR_MST1_REG 0x44
18 #define FW_DDR_MST6_REG 0x58
19 #define FW_DDR_MST7_REG 0x5c
20 #define FW_DDR_MST11_REG 0x6c
21 #define FW_DDR_MST14_REG 0x78
22 #define FW_DDR_MST16_REG 0x80
23 #define FW_DDR_MST_REG 0xf0
25 #define VENC_GRF_BASE 0xff320000
26 #define VENC_GRF_CON1 0x4
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3308.dtsi35 #size-cells = <0>;
37 cpu0: cpu@0 {
40 reg = <0x0 0x0>;
47 reg = <0x0 0x1>;
54 reg = <0x0 0x2>;
61 reg = <0x0 0x3>;
79 #clock-cells = <0>;
101 reg = <0x0 0xff010000 0x0 0x10000>;
121 #clock-cells = <0>;
129 reg = <0x0 0xff000000 0x0 0x10000>;
[all …]
H A D.rk3308-evb.dtb.dts.tmp
H A Dpx30.dtsi34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0 0x0>;
46 reg = <0x0 0x1>;
52 reg = <0x0 0x2>;
58 reg = <0x0 0x3>;
74 reg = <0x0 0xff2a0000 0x0 0x1000>;
94 #clock-cells = <0>;
112 #clock-cells = <0>;
119 reg = <0x0 0xff000000 0x0 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3308.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
73 reg = <0x0 0x1>;
83 reg = <0x0 0x2>;
93 reg = <0x0 0x3>;
106 arm,psci-suspend-param = <0x0010000>;
123 rockchip,low-temp = <0>;
128 0 1296 50000
136 0 54000 0
[all …]
H A Dpx30.dtsi49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
66 reg = <0x0 0x1>;
78 reg = <0x0 0x2>;
90 reg = <0x0 0x3>;
105 arm,psci-suspend-param = <0x0010000>;
114 arm,psci-suspend-param = <0x1010000>;
127 rockchip,low-temp = <0>;
131 0 1512 50000
[all …]