Home
last modified time | relevance | path

Searched +full:0 +full:xff200000 (Results 1 – 25 of 33) sorted by relevance

12

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Daltera-pcie-msi.txt18 msi0: msi@0xFF200000 {
20 reg = <0xFF200000 0x00000010
21 0xFF200010 0x00000080>;
24 interrupts = <0 42 4>;
H A Dqcom,pcie.txt261 reg = <0x1b500000 0x1000
262 0x1b502000 0x80
263 0x1b600000 0x100
264 0x0ff00000 0x100000>;
267 linux,pci-domain = <0>;
268 bus-range = <0x00 0xff>;
272 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
273 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
277 interrupt-map-mask = <0 0 0 0x7>;
278 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_ac5.h10 #define SOCFPGA_STM_ADDRESS 0xfc000000
11 #define SOCFPGA_DAP_ADDRESS 0xff000000
12 #define SOCFPGA_EMAC0_ADDRESS 0xff700000
13 #define SOCFPGA_EMAC1_ADDRESS 0xff702000
14 #define SOCFPGA_SDMMC_ADDRESS 0xff704000
15 #define SOCFPGA_QSPI_ADDRESS 0xff705000
16 #define SOCFPGA_GPIO0_ADDRESS 0xff708000
17 #define SOCFPGA_GPIO1_ADDRESS 0xff709000
18 #define SOCFPGA_GPIO2_ADDRESS 0xff70a000
19 #define SOCFPGA_L3REGS_ADDRESS 0xff800000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpio/
H A Dgpio-altera.txt36 reg = <0xff200000 0x10>;
37 interrupts = <0 45 4>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dhisilicon,hi3660-usb3.yaml19 const: 0
50 reg = <0x0 0xff200000 0x0 0x1000>;
54 #phy-cells = <0>;
57 hisilicon,eye-diagram-param = <0x22466e4>;
/OK3568_Linux_fs/kernel/drivers/staging/hikey9xx/
H A Dphy-hi3670-usb3.yaml19 const: 0
60 reg = <0x0 0xff200000 0x0 0x1000>;
64 #phy-cells = <0>;
68 hisilicon,eye-diagram-param = <0xfdfee4>;
69 hisilicon,tx-vboost-lvl = <0x5>;
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/include/mach/
H A Dpalmtx.h71 #define PALMTX_PCMCIA_PHYS 0x28000000
72 #define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000)
73 #define PALMTX_PCMCIA_SIZE 0x100000
75 #define PALMTX_PHYS_RAM_START 0xa0000000
76 #define PALMTX_PHYS_IO_START 0x40000000
78 #define PALMTX_STR_BASE 0xa0200000
80 #define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
85 #define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000)
86 #define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000)
95 #define PALMTX_BAT_MAX_CURRENT 0 /* unknown */
[all …]
/OK3568_Linux_fs/u-boot/arch/sh/include/asm/
H A Dcpu_sh7750.h15 #define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
18 #define CCR_CACHE_INIT 0x0000090B
22 #define PTEH 0xFF000000
23 #define PTEL 0xFF000004
24 #define TTB 0xFF000008
25 #define TEA 0xFF00000C
26 #define MMUCR 0xFF000010
27 #define BASRA 0xFF000014
28 #define BASRB 0xFF000018
29 #define CCR 0xFF00001C
[all …]
H A Dcpu_sh7780.h12 #define CCR_CACHE_INIT 0x0000090b
15 #define TRA 0xFF000020
16 #define EXPEVT 0xFF000024
17 #define INTEVT 0xFF000028
20 #define PTEH 0xFF000000
21 #define PTEL 0xFF000004
22 #define TTB 0xFF000008
23 #define TEA 0xFF00000C
24 #define MMUCR 0xFF000010
25 #define PASCR 0xFF000070
[all …]
H A Dcpu_sh7722.h13 #define CCR_CACHE_INIT 0x0000090d
16 #define TRA 0xFF000020
17 #define EXPEVT 0xFF000024
18 #define INTEVT 0xFF000028
21 #define PTEH 0xFF000000
22 #define PTEL 0xFF000004
23 #define TTB 0xFF000008
24 #define TEA 0xFF00000C
25 #define MMUCR 0xFF000010
26 #define PASCR 0xFF000070
[all …]
/OK3568_Linux_fs/kernel/arch/sh/kernel/cpu/sh4a/
H A Dubc.c15 #define UBC_CBR(idx) (0xff200000 + (0x20 * idx))
16 #define UBC_CRR(idx) (0xff200004 + (0x20 * idx))
17 #define UBC_CAR(idx) (0xff200008 + (0x20 * idx))
18 #define UBC_CAMR(idx) (0xff20000c + (0x20 * idx))
20 #define UBC_CCMFR 0xff200600
21 #define UBC_CBCR 0xff200620
25 #define UBC_CRR_BIE (1 << 0)
28 #define UBC_CBR_CE (1 << 0)
40 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
41 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/sun3/
H A Dconfig.c61 clock_va = (char *) 0xfe06000; /* dark */ in sun3_init()
62 sun3_intreg = (unsigned char *) 0xfe0a000; /* magic */ in sun3_init()
68 enable_register |= 0x50; /* Enable FPU */ in sun3_init()
76 memset(sun3_reserved_pmeg, 0, sizeof(sun3_reserved_pmeg)); in sun3_init()
81 for (i=0; i<8; i++) /* Kernel PMEGs */ in sun3_init()
123 m68k_setup_node(0); in sun3_bootmem_alloc()
144 memory_start = ((((unsigned long)_end) + 0x2000) & ~0x1fff); in config_sun3()
149 m68k_memory[0].size=*(romvec->pv_sun3mem); in config_sun3()
175 .start = 0xff200000,
176 .end = 0xff200021,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.txt210 bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
218 reg = <0xff706000 0x1000
219 0xffb90000 0x20>;
220 interrupts = <0 175 4>;
225 reg = <0xff400000 0x100000>;
241 reg = <0xff500000 0x10000>;
250 fragment@0 {
260 ranges = <0x20000 0xff200000 0x100000>,
261 <0x0 0xc0000000 0x20000000>;
265 reg = <0x10040 0x20>;
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A DP1023RDB.h14 #define CONFIG_SYS_TEXT_BASE 0xeff40000
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
52 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
53 #define CONFIG_SYS_MEMTEST_END 0x02000000
56 #define CONFIG_SYS_LBC_LBCR 0x00000000
61 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
70 #define CONFIG_SYS_SPD_BUS_NUM 0
71 #define SPD_EEPROM_ADDRESS 0x50
77 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
78 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
[all …]
/OK3568_Linux_fs/kernel/include/linux/ssb/
H A Dssb_regs.h9 #define SSB_SDRAM_BASE 0x00000000U /* Physical SDRAM */
10 #define SSB_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
11 #define SSB_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
12 #define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
13 #define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */
14 #define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */
16 #define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
17 #define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */
19 #define SSB_EXTIF_BASE 0x1f000000U /* External Interface region base address */
20 #define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/hisilicon/
H A Dhi3660.dtsi25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
75 reg = <0x0 0x1>;
88 reg = <0x0 0x2>;
101 reg = <0x0 0x3>;
114 reg = <0x0 0x100>;
128 reg = <0x0 0x101>;
141 reg = <0x0 0x102>;
154 reg = <0x0 0x103>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1106.dtsi55 #size-cells = <0>;
60 reg = <0xf00>;
106 rockchip,wake-irq = <0>;
107 rockchip,irq-mode-enable = <0>;
133 size = <0x800000>;
211 thermal-sensors = <&tsadc 0>;
213 threshold: trip-point-0 {
244 #clock-cells = <0>;
249 reg = <0xff000000 0x68000>;
258 offset = <0x20200>;
[all …]
H A Drk3399.dtsi42 #size-cells = <0>;
70 cpu_l0: cpu@0 {
73 reg = <0x0 0x0>;
82 reg = <0x0 0x1>;
90 reg = <0x0 0x2>;
98 reg = <0x0 0x3>;
106 reg = <0x0 0x100>;
115 reg = <0x0 0x101>;
164 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
165 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
[all …]
H A Dpx30.dtsi34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0 0x0>;
46 reg = <0x0 0x1>;
52 reg = <0x0 0x2>;
58 reg = <0x0 0x3>;
74 reg = <0x0 0xff2a0000 0x0 0x1000>;
94 #clock-cells = <0>;
112 #clock-cells = <0>;
119 reg = <0x0 0xff000000 0x0 0x1000>;
[all …]
H A Drk3562.dtsi71 #clock-cells = <0>;
78 #clock-cells = <0>;
85 reg = <0 0xff100324 0 0x10>;
89 #clock-cells = <0>;
94 reg = <0 0xff100328 0 0x10>;
98 #clock-cells = <0>;
103 reg = <0 0xff10032c 0 0x10>;
107 #clock-cells = <0>;
112 reg = <0 0xff100334 0 0x10>;
116 #clock-cells = <0>;
[all …]
H A Drk3528.dtsi57 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
99 reg = <0x0 0x2>;
109 reg = <0x0 0x3>;
122 arm,psci-suspend-param = <0x0010000>;
132 arm,psci-suspend-param = <0x0010000>;
149 0 1310 0
158 rockchip,pvtm-offset = <0x18>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drv1106.dtsi72 #clock-cells = <0>;
76 rkvenc_pvtpll: pvtpll-0 {
80 #clock-cells = <0>;
87 #clock-cells = <0>;
94 #clock-cells = <0>;
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0x0>;
118 rockchip,pvtpll-avg-offset = <0x4001c>;
227 rockchip,wake-irq = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/wlan-ng/
H A Dprism2fw.c65 #define S3ADDR_PLUG (0xff000000UL)
66 #define S3ADDR_CRC (0xff100000UL)
67 #define S3ADDR_INFO (0xff200000UL)
68 #define S3ADDR_START (0xff400000UL)
204 * 0 - success
205 * ~0 - failure
215 PRISM2_USB_FWFILE, &udev->dev) != 0) { in prism2_fwtry()
229 return 0; in prism2_fwtry()
242 * 0 - success
243 * ~0 - failure
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3528.dtsi63 #clock-cells = <0>;
70 #clock-cells = <0>;
71 clock-frequency = <0>;
77 #clock-cells = <0>;
78 clock-frequency = <0>;
84 reg = <0 0xff340014 0 0x4>;
86 #clock-cells = <0>;
94 reg = <0 0xff320004 0 0x4>;
96 #clock-cells = <0>;
105 #size-cells = <0>;
[all …]

12