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Searched +full:0 +full:xfec10000 (Results 1 – 13 of 13) sorted by relevance

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/
H A Drenesas,bsc.yaml57 ranges = <0 0 0x20000000>;
58 reg = <0xfec10000 0x400>;
59 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
/OK3568_Linux_fs/kernel/arch/sh/include/mach-ecovec24/mach/
H A Dpartner-jet-setup.txt9 LIST "> RD zImage, 0xa8800000"
10 LIST "> G=0xa8800000"
14 LIST "> RD romImage, 0"
18 EW 0xa4520004, 0xa507
21 ED 0xff000010, 0x00000004
24 ED 0xa4150024, 0x00004000
25 ED 0xa4150000, 0x8E003508
30 ED 0xff800020, 0xa5a50000
31 ED 0xfec10000, 0x00001013
32 ED 0xfec10004, 0x11110400
[all …]
/OK3568_Linux_fs/kernel/arch/sh/include/mach-kfr2r09/mach/
H A Dpartner-jet-setup.txt8 LIST "> RD zImage, 0xa8800000"
9 LIST "> G=0xa8800000"
13 LIST "> RD romImage, 0"
18 EW 0xa4520004, 0xa507
21 ED 0xff00001c, 0x00000800
24 ED 0xff000010, 0x00000004
27 ED 0xff800020, 0xa5a50001
28 ED 0xfec10000, 0x0000001b
33 ED 0xa4150004, 0x00000050
34 ED 0xa4150000, 0x91053508
[all …]
/OK3568_Linux_fs/u-boot/arch/sh/include/asm/
H A Dcpu_sh7723.h13 #define CCR_CACHE_INIT 0x0000090d
16 #define TRA 0xFF000020
17 #define EXPEVT 0xFF000024
18 #define INTEVT 0xFF000028
21 #define PTEH 0xFF000000
22 #define PTEL 0xFF000004
23 #define TTB 0xFF000008
24 #define TEA 0xFF00000C
25 #define MMUCR 0xFF000010
26 #define PASCR 0xFF000070
[all …]
H A Dcpu_sh7724.h13 #define CCR_CACHE_INIT 0x0000090d
16 #define TRA 0xFF000020
17 #define EXPEVT 0xFF000024
18 #define INTEVT 0xFF000028
21 #define PTEH 0xFF000000
22 #define PTEL 0xFF000004
23 #define TTB 0xFF000008
24 #define TEA 0xFF00000C
25 #define MMUCR 0xFF000010
26 #define PASCR 0xFF000070
[all …]
H A Dcpu_sh7722.h13 #define CCR_CACHE_INIT 0x0000090d
16 #define TRA 0xFF000020
17 #define EXPEVT 0xFF000024
18 #define INTEVT 0xFF000028
21 #define PTEH 0xFF000000
22 #define PTEL 0xFF000004
23 #define TTB 0xFF000008
24 #define TEA 0xFF00000C
25 #define MMUCR 0xFF000010
26 #define PASCR 0xFF000070
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rmobile/include/mach/
H A Dr8a7740.h14 #define MERAM_BASE 0xE5580000
15 #define DDRP_BASE 0xC12A0000
16 #define HPB_BASE 0xE6000000
17 #define RWDT0_BASE 0xE6020000
18 #define RWDT1_BASE 0xE6030000
19 #define GPIO_BASE 0xE6050000
20 #define CMT1_BASE 0xE6138000
21 #define CPG_BASE 0xE6150000
22 #define SYSC_BASE 0xE6180000
23 #define SDHI0_BASE 0xE6850000
[all …]
H A Dsh73a0.h5 #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
6 #define MERAM_BASE (0xE5580000)
9 #define GIC_BASE (0xF0000100)
13 #define LIFEC_SEC_SRC (0xE6110008)
16 #define RWDT_BASE (0xE6020000)
19 #define HPB_BASE (0xE6001010)
22 #define HPBSCR_BASE (0xE6001600)
25 #define SBSC1_BASE (0xFE400000)
26 #define SDMRA1A (SBSC1_BASE + 0x100000)
27 #define SDMRA2A (SBSC1_BASE + 0x1C0000)
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dr8a73a4.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
65 reg = <0 0xe6790000 0 0x10000>;
71 reg = <0 0xe67a0000 0 0x10000>;
86 reg = <0 0xe6700020 0 0x89e0>;
121 #size-cells = <0>;
123 reg = <0 0xe60b0000 0 0x428>;
133 reg = <0 0xe6130000 0 0x1004>;
[all …]
H A Dsh73a0.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/
H A DKconfig.debug138 0x80000000 | 0xf0000000 | UART0
139 0x80004000 | 0xf0004000 | UART1
140 0x80008000 | 0xf0008000 | UART2
141 0x8000c000 | 0xf000c000 | UART3
142 0x80010000 | 0xf0010000 | UART4
143 0x80014000 | 0xf0014000 | UART5
144 0x80018000 | 0xf0018000 | UART6
145 0x8001c000 | 0xf001c000 | UART7
146 0x80020000 | 0xf0020000 | UART8
147 0x80024000 | 0xf0024000 | UART9
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3588s.dtsi56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
102 reg = <0x100>;
110 reg = <0x200>;
118 reg = <0x300>;
126 reg = <0x400>;
134 reg = <0x500>;
142 reg = <0x600>;
150 reg = <0x700>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3588s.dtsi89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #clock-cells = <0>;
110 reg = <0 0xfd7c08ec 0 0x10>;
114 #clock-cells = <0>;
119 reg = <0 0xfd7c08b0 0 0x10>;
123 #clock-cells = <0>;
128 reg = <0 0xfd7c08dc 0 0x10>;
132 #clock-cells = <0>;
137 reg = <0 0xfd7c08a8 0 0x10>;
[all …]