Searched +full:0 +full:xfdd00000 (Results 1 – 20 of 20) sorted by relevance
62 "-sram@[0-9a-f]+$":81 reg = <0xfdd00000 0x2000>,82 <0xfec00000 0x180000>;93 ranges = <0 0xfec00000 0x100000>;95 gmu-sram@0 {96 reg = <0x0 0x100000>;
42 reg = <0x0 0xfdd00000 0x0 0x1000>;49 reg = <0x0 0xfdd20000 0x0 0x1000>;60 reg = <0x0 0xfe650000 0x0 0x100>;
50 reg = <0xfdb00000 0x10000>;63 iommus = <&gpu_iommu 0>;69 reg = <0xfdd00000 0x2000>,70 <0xfec00000 0x180000>;82 gpu_sram: gpu-sram@0 {83 reg = <0x0 0x100000>;84 ranges = <0 0 0xfec00000 0x100000>;98 reg = <0x5000000 0x40000>, <0x509e000 0x10>;108 iommus = <&adreno_smmu 0>;
19 * e0000000 @runtime 128M PCIe-0 Memory space23 * f2000000 fee00000 1M PCIe-0 I/O space27 #define DOVE_CESA_PHYS_BASE 0xc800000028 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)31 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe000000034 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe800000037 #define DOVE_BOOTROM_PHYS_BASE 0xf800000040 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf000000041 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)44 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000[all …]
18 #define CONFIG_SYS_TEXT_BASE 0xeff4000022 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef54 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */55 #define CONFIG_SYS_MEMTEST_END 0x0040000061 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC000072 #define CONFIG_SYS_DCSRBAR 0xf000000073 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull79 #define CONFIG_SYS_DDR_SDRAM_BASE 0x0000000091 #define CONFIG_SYS_FLASH_BASE 0xe0000000[all …]
30 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc47 #define CONFIG_SYS_TEXT_BASE 0xeff4000062 #define CONFIG_SYS_MMC_ENV_DEV 063 #define CONFIG_ENV_SIZE 0x200077 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef89 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */90 #define CONFIG_SYS_MEMTEST_END 0x0040000098 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)106 #define CONFIG_SYS_DCSRBAR 0xf0000000107 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull[all …]
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc52 #define CONFIG_SYS_TEXT_BASE 0xeff4000056 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc77 #define CONFIG_ENV_SPI_BUS 078 #define CONFIG_ENV_SPI_CS 080 #define CONFIG_ENV_SPI_MODE 0[all …]
32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc45 #define CONFIG_SYS_TEXT_BASE 0xeff4000049 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc75 #define CONFIG_ENV_SPI_BUS 076 #define CONFIG_ENV_SPI_CS 078 #define CONFIG_ENV_SPI_MODE 079 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */80 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */81 #define CONFIG_ENV_SECT_SIZE 0x1000084 #define CONFIG_SYS_MMC_ENV_DEV 0[all …]
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc26 #define CONFIG_SYS_TEXT_BASE 0x0020100027 #define CONFIG_SPL_TEXT_BASE 0xFFFD800028 #define CONFIG_SPL_PAD_TO 0x4000029 #define CONFIG_SPL_MAX_SIZE 0x2800030 #define RESET_VECTOR_OFFSET 0x27FFC31 #define BOOT_PAGE_OFFSET 0x2700034 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x0020000038 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000[all …]
35 #define CONFIG_SYS_TEXT_BASE 0x0020100036 #define CONFIG_SPL_TEXT_BASE 0xFFFD800037 #define CONFIG_SPL_PAD_TO 0x4000038 #define CONFIG_SPL_MAX_SIZE 0x2800039 #define RESET_VECTOR_OFFSET 0x27FFC40 #define BOOT_PAGE_OFFSET 0x2700049 #define CONFIG_SYS_NAND_U_BOOT_DST 0x0020000050 #define CONFIG_SYS_NAND_U_BOOT_START 0x0020000058 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)[all …]
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc22 #define CONFIG_SYS_TEXT_BASE 0x0020100023 #define CONFIG_SPL_TEXT_BASE 0xFFFD800024 #define CONFIG_SPL_PAD_TO 0x4000025 #define CONFIG_SPL_MAX_SIZE 0x2800026 #define RESET_VECTOR_OFFSET 0x27FFC27 #define BOOT_PAGE_OFFSET 0x2700029 #define CONFIG_SYS_NAND_U_BOOT_DST 0x0020000030 #define CONFIG_SYS_NAND_U_BOOT_START 0x0020000044 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)[all …]
36 #define CONFIG_SYS_TEXT_BASE 0x0020100037 #define CONFIG_SPL_TEXT_BASE 0xFFFD800038 #define CONFIG_SPL_PAD_TO 0x4000039 #define CONFIG_SPL_MAX_SIZE 0x2800040 #define RESET_VECTOR_OFFSET 0x27FFC41 #define BOOT_PAGE_OFFSET 0x2700050 #define CONFIG_SYS_NAND_U_BOOT_DST 0x0020000051 #define CONFIG_SYS_NAND_U_BOOT_START 0x0020000059 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)[all …]
38 #define CONFIG_SYS_TEXT_BASE 0x3000100039 #define CONFIG_SPL_TEXT_BASE 0xFFFD800040 #define CONFIG_SPL_PAD_TO 0x4000041 #define CONFIG_SPL_MAX_SIZE 0x2800042 #define RESET_VECTOR_OFFSET 0x27FFC43 #define BOOT_PAGE_OFFSET 0x2700052 #define CONFIG_SYS_NAND_U_BOOT_DST 0x3000000053 #define CONFIG_SYS_NAND_U_BOOT_START 0x3000000065 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)[all …]
26 #define CONFIG_SYS_TEXT_BASE 0x3000100027 #define CONFIG_SPL_TEXT_BASE 0xFFFD800028 #define CONFIG_SPL_PAD_TO 0x4000029 #define CONFIG_SPL_MAX_SIZE 0x2800035 #define RESET_VECTOR_OFFSET 0x27FFC36 #define BOOT_PAGE_OFFSET 0x2700050 #define CONFIG_SYS_NAND_U_BOOT_DST 0x3000000051 #define CONFIG_SYS_NAND_U_BOOT_START 0x3000000078 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)[all …]
42 #define CONFIG_SYS_TEXT_BASE 0x0020100043 #define CONFIG_SPL_TEXT_BASE 0xFFFD800044 #define CONFIG_SPL_PAD_TO 0x4000045 #define CONFIG_SPL_MAX_SIZE 0x2800046 #define RESET_VECTOR_OFFSET 0x27FFC47 #define BOOT_PAGE_OFFSET 0x2700056 #define CONFIG_SYS_NAND_U_BOOT_DST 0x0020000057 #define CONFIG_SYS_NAND_U_BOOT_START 0x0020000069 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)[all …]
22 printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \24 } while (0)27 #define PCIE_SNPS_DBI_BASE 0xf500000028 #define PCIE_SNPS_APB_BASE 0xfe15000029 #define PCIE_SNPS_IATU_BASE 0xa4030000031 #define PCI_RESBAR 0x2e833 #define PCIE_SNPS_DBI_BASE 0xf600000034 #define PCIE_SNPS_APB_BASE 0xfe28000035 #define PCIE_SNPS_IATU_BASE 0x3c0b0000037 #define PCI_RESBAR 0x2b8[all …]
25 reg = <0x08000000 0x5100000>;30 reg = <0x0d100000 0x100000>;35 reg = <0x0d200000 0xa00000>;40 reg = <0x0dc00000 0x1900000>;45 reg = <0x0f500000 0x500000>;50 reg = <0xfa00000 0x200000>;55 reg = <0x0fc00000 0x160000>;60 reg = <0x0fd60000 0x20000>;66 reg = <0x0fd80000 0x180000>;75 #size-cells = <0>;[all …]
58 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0x0 0x0>;72 reg = <0x0 0x100>;81 reg = <0x0 0x200>;90 reg = <0x0 0x300>;160 thermal-sensors = <&tsadc 0>;192 #clock-cells = <0>;199 #clock-cells = <0>;204 #clock-cells = <0>;[all …]
66 #size-cells = <0>;68 cpu0: cpu@0 {71 reg = <0x0 0x0>;73 clocks = <&scmi_clk 0>;83 reg = <0x0 0x100>;85 clocks = <&scmi_clk 0>;93 reg = <0x0 0x200>;95 clocks = <&scmi_clk 0>;103 reg = <0x0 0x300>;105 clocks = <&scmi_clk 0>;[all …]