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/OK3568_Linux_fs/kernel/arch/arm/crypto/
H A Dpoly1305-core.S_shipped31 cmp r1,#0
32 str r3,[r0,#0] @ zero hash value
43 moveq r0,#0
54 ldrb r4,[r1,#0]
55 mov r10,#0x0fffffff
57 and r3,r10,#-4 @ 0x0ffffffc
113 str r4,[r0,#0]
124 mov r0,#0
133 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
166 mov r2,#0
[all …]
H A Dpoly1305-armv4.pl28 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
38 ($ctx,$inp,$len,$padbit)=map("r$_",(0..3));
71 cmp $inp,#0
72 str r3,[$ctx,#0] @ zero hash value
83 moveq r0,#0
94 ldrb r4,[$inp,#0]
95 mov r10,#0x0fffffff
97 and r3,r10,#-4 @ 0x0ffffffc
153 str r4,[$ctx,#0]
164 mov r0,#0
[all …]
/OK3568_Linux_fs/u-boot/board/sbc8548/
H A Dtlb.c14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-spear/include/mach/
H A Dspear.h21 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
22 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
23 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
25 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
28 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
29 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
32 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
33 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
34 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
35 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/mali400/mali/platform/arm/
H A Darm.c38 static int mali_core_scaling_enable = 0;
48 #define SECURE_MODE_CONTROL_HANDLER 0x6F02006C
53 * 0: success
54 * non-0: failure.
59 u32 phys_offset = SECURE_MODE_CONTROL_HANDLER & 0x00001FFF; in mali_gpu_reset_and_secure_mode_enable_juno()
66 return 0; in mali_gpu_reset_and_secure_mode_enable_juno()
77 u32 phys_offset = SECURE_MODE_CONTROL_HANDLER & 0x00001FFF; in mali_gpu_reset_and_secure_mode_disable_juno()
80 iowrite32(0, ((u8 *)secure_mode_mapped_addr) + phys_offset); in mali_gpu_reset_and_secure_mode_disable_juno()
82 if (0 == (u32)ioread32(((u8 *)secure_mode_mapped_addr) + phys_offset)) { in mali_gpu_reset_and_secure_mode_disable_juno()
84 return 0; in mali_gpu_reset_and_secure_mode_disable_juno()
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dprobes.h13 #define BREAKPOINT_INSTRUCTION 0x7fe00008 /* trap */
16 #define IS_TW(instr) (((instr) & 0xfc0007fe) == 0x7c000008)
17 #define IS_TD(instr) (((instr) & 0xfc0007fe) == 0x7c000088)
18 #define IS_TDI(instr) (((instr) & 0xfc000000) == 0x08000000)
19 #define IS_TWI(instr) (((instr) & 0xfc000000) == 0x0c000000)
/OK3568_Linux_fs/kernel/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
30 #define XBUS_SIZE 0x00100000
[all …]
/OK3568_Linux_fs/u-boot/board/micronas/vct/
H A Debi_nor_flash.c13 addr &= ~0xFC000000; in ebi_read()
25 addr &= ~0xFC000000; in ebi_write_u16()
35 u32 counter = 0; in ebi_write_u16()
37 if (counter++ > 0xFFFFFF) in ebi_write_u16()
42 return 0; in ebi_write_u16()
47 return ((ebi_read(addr) >> 16) & 0xFFFF); in ebi_read_u16()
54 if (addr & 0x1) in ebi_read_u8()
55 return val & 0xff; in ebi_read_u8()
57 return (val >> 8) & 0xff; in ebi_read_u8()
65 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_nor_flash()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-spear/
H A Dspear3xx.c28 .bus_id = 0,
60 * 0xD0000000 0xFD000000
61 * 0xFC000000 0xFC000000
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dstorcenter.dts30 #size-cells = <0>;
32 PowerPC,8241@0 {
34 reg = <0>;
37 bus-frequency = <0>; /* from bootwrapper */
47 reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
55 store-gathering = <0>; /* 0 == off, !0 == on */
56 ranges = <0x0 0xfc000000 0x100000>;
57 reg = <0xfc000000 0x100000>; /* EUMB */
58 bus-frequency = <0>; /* fixed by loader */
62 #size-cells = <0>;
[all …]
H A DkuroboxHG.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x8000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A DkuroboxHD.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x4000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A Do2d.dts15 memory@0 {
16 reg = <0x00000000 0x08000000>; // 128MB
20 ranges = <0 0 0xfc000000 0x02000000
21 3 0 0xe3000000 0x00100000>;
23 flash@0,0 {
25 reg = <0 0 0x02000000>;
33 reg = <0x00060000 0x00260000>;
39 reg = <0x002c0000 0x01d40000>;
H A Do3dnt.dts15 memory@0 {
16 reg = <0x00000000 0x04000000>; // 64MB
20 ranges = <0 0 0xfc000000 0x01000000
21 3 0 0xe3000000 0x00100000>;
23 flash@0,0 {
25 reg = <0 0 0x01000000>;
33 reg = <0x00060000 0x00260000>;
40 reg = <0x002c0000 0x00d40000>;
H A Do2dnt2.dts15 memory@0 {
16 reg = <0x00000000 0x08000000>; // 128MB
20 ranges = <0 0 0xfc000000 0x02000000
21 3 0 0xe3000000 0x00100000>;
23 flash@0,0 {
25 reg = <0 0 0x02000000>;
33 reg = <0x00060000 0x00260000>;
40 reg = <0x002c0000 0x01d40000>;
/OK3568_Linux_fs/kernel/include/linux/ssb/
H A Dssb_driver_pci.h13 #define SSB_PCICORE_CTL 0x0000 /* PCI Control */
14 #define SSB_PCICORE_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
15 #define SSB_PCICORE_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
16 #define SSB_PCICORE_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
17 #define SSB_PCICORE_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
18 #define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */
19 #define SSB_PCICORE_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
20 #define SSB_PCICORE_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
21 #define SSB_PCICORE_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus…
22 #define SSB_PCICORE_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
[all …]
/OK3568_Linux_fs/kernel/drivers/thermal/qcom/
H A Dtsens-v0_1.c10 #define SROT_CTRL_OFF 0x0000
13 #define TM_INT_EN_OFF 0x0000
14 #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
15 #define TM_Sn_STATUS_OFF 0x0030
16 #define TM_TRDY_OFF 0x005c
19 #define MSM8916_BASE0_MASK 0x0000007f
20 #define MSM8916_BASE1_MASK 0xfe000000
21 #define MSM8916_BASE0_SHIFT 0
24 #define MSM8916_S0_P1_MASK 0x00000f80
25 #define MSM8916_S1_P1_MASK 0x003e0000
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/m53017evb/
H A DREADME71 CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
115 Flash: 0x00000000-0x3FFFFFFF (1024MB)
116 DDR: 0x40000000-0x7FFFFFFF (1024MB)
117 SRAM: 0x80000000-0x8FFFFFFF (256MB)
118 IP: 0xFC000000-0xFFFFFFFF (256MB)
122 Flash0: 0x00000000-0x00FFFFFF (16MB)
123 DDR: 0x40000000-0x4FFFFFFF (256MB)
124 SRAM: 0x80000000-0x80007FFF (32KB)
125 IP: 0xFC000000-0xFC0FFFFF (64KB)
147 CPU: Freescale MCF53015 (Mask:76 Version:0)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dspear-thermal.txt12 reg = <0xfc000000 0x1000>;
13 st,thermal-flags = <0x7000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dsdhci-spear.txt16 reg = <0xfc000000 0x1000>;
17 cd-gpios = <&gpio0 6 0>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rtc/
H A Dspear-rtc.txt12 reg = <0xfc000000 0x1000>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv50/
H A Dhandles.h10 #define NV50_DISP_HANDLE_SYNCBUF 0xf0000000
11 #define NV50_DISP_HANDLE_VRAM 0xf0000001
13 #define NV50_DISP_HANDLE_WNDW_CTX(kind) (0xfb000000 | kind)
14 #define NV50_DISP_HANDLE_CRC_CTX(head, i) (0xfc000000 | head->base.index << 1 | i)
/OK3568_Linux_fs/u-boot/board/rockchip/evb_rk3588/
H A Devb_rk3588.c16 .base = 0xfc000000,
18 .index = 0,
25 dwc3_uboot_handle_interrupt(0); in usb_gadget_handle_interrupts()
26 return 0; in usb_gadget_handle_interrupts()

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