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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/
H A Dhisilicon,hi6220-reset.txt22 reg = <0x0 0xf7030000 0x0 0x2000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dhi6220-clock.txt37 reg = <0x0 0xf7030000 0x0 0x2000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml58 cpu 2, reg + 0x4;
59 cpu 3, reg + 0x8;
99 ranges = <0 0x802000 0x1000>;
100 reg = <0x802000 0x1000>;
102 smp-offset = <0x31c>;
103 resume-offset = <0x308>;
104 reboot-offset = <0x4>;
106 clock: clock@0 {
108 reg = <0 0x10000>;
116 reg = <0x10000000 0x1000>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dhi6220.dtsi23 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
66 reg = <0x0 0x1>;
73 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
87 reg = <0x0 0x100>;
94 reg = <0x0 0x101>;
101 reg = <0x0 0x102>;
108 reg = <0x0 0x103>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-hi6220/
H A Dhi6220.h13 #define HI6220_MMC0_BASE 0xF723D000
14 #define HI6220_MMC1_BASE 0xF723E000
16 #define HI6220_UART0_BASE 0xF8015000
17 #define HI6220_UART3_BASE 0xF7113000
19 #define HI6220_PMUSSI_BASE 0xF8000000
21 #define HI6220_PERI_BASE 0xF7030000
24 u32 ctrl1; /*0x0*/
39 u32 ddr_ctrl0; /*0x50*/
43 u32 stat1; /*0x94*/
47 u32 clk0_en; /*0x200*/
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/hisilicon/
H A Dhi6220.dtsi27 #size-cells = <0>;
66 arm,psci-suspend-param = <0x0010000>;
75 arm,psci-suspend-param = <0x1010000>;
83 cpu0: cpu@0 {
86 reg = <0x0 0x0>;
89 clocks = <&stub_clock 0>;
99 reg = <0x0 0x1>;
102 clocks = <&stub_clock 0>;
112 reg = <0x0 0x2>;
115 clocks = <&stub_clock 0>;
[all …]