Home
last modified time | relevance | path

Searched +full:0 +full:xf0000000 (Results 1 – 25 of 1010) sorted by relevance

12345678910>>...41

/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/book3s/32/
H A Dkup.h12 addi \gpr1, \gpr1, 0x111 /* next VSID */
13 rlwinm \gpr1, \gpr1, 0, 0xf0ffffff /* clear VSID overflow */
14 addis \gpr2, \gpr2, 0x1000 /* address of next segment */
22 li \gpr2, 0
33 li \gpr2, 0
36 rlwinm \gpr1, \gpr1, 0, ~SR_NX /* Clear Nx */
45 addi \gpr1, \gpr1, 0x111 /* next VSID */
46 rlwinm \gpr1, \gpr1, 0, 0xf0ffffff /* clear VSID overflow */
47 addis \gpr2, \gpr2, 0x1000 /* address of next segment */
55 rlwinm. \gpr3, \gpr2, 28, 0xf0000000
[all …]
/OK3568_Linux_fs/kernel/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler.h24 0xbf820001, 0xbf820121,
25 0xb8f4f802, 0x89748674,
26 0xb8f5f803, 0x8675ff75,
27 0x00000400, 0xbf850017,
28 0xc00a1e37, 0x00000000,
29 0xbf8c007f, 0x87777978,
30 0xbf840005, 0x8f728374,
31 0xb972e0c2, 0xbf800002,
32 0xb9740002, 0xbe801d78,
33 0xb8f5f803, 0x8675ff75,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/phydm/halrf/rtl8822c/
H A Dhalrf_8822c.c42 u8 path = 0x0; in halrf_rf_lna_setting_8822c()
44 for (path = 0x0; path < 2; path++) in halrf_rf_lna_setting_8822c()
48 0x1); in halrf_rf_lna_setting_8822c()
50 RFREGOFFSETMASK, 0x00003); in halrf_rf_lna_setting_8822c()
52 RFREGOFFSETMASK, 0x00064); in halrf_rf_lna_setting_8822c()
54 RFREGOFFSETMASK, 0x0afce); in halrf_rf_lna_setting_8822c()
56 0x0); in halrf_rf_lna_setting_8822c()
60 0x1); in halrf_rf_lna_setting_8822c()
62 RFREGOFFSETMASK, 0x00003); in halrf_rf_lna_setting_8822c()
64 RFREGOFFSETMASK, 0x00064); in halrf_rf_lna_setting_8822c()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-ep93xx/
H A Dsoc.h19 * the synchronous boot mode is selected. When ASDO is "0" (i.e
23 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
24 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
25 * decoded at 0xf0000000.
34 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
35 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
36 #define EP93XX_CS1_PHYS_BASE 0x10000000
37 #define EP93XX_CS2_PHYS_BASE 0x20000000
38 #define EP93XX_CS3_PHYS_BASE 0x30000000
39 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
[all …]
/OK3568_Linux_fs/u-boot/drivers/usb/host/
H A Dehci-rmobile.c17 0xC6700000
21 0xEE080000, /* USB0 (EHCI) */
22 0xEE0A0000, /* USB1 */
23 0xEE0C0000, /* USB2 */
28 0xEE080000, /* USB0 (EHCI) */
29 0xEE0C0000, /* USB1 */
43 writel(0, &ahbcom_pci->ahb_bus_ctr); in ehci_hcd_stop()
47 for (i = 100; i > 0; i--) { in ehci_hcd_stop()
59 return 0; in ehci_hcd_stop()
76 if (index == 0) in ehci_hcd_init()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-shmobile/
H A Dsetup-r8a7779.c19 /* 2M identity mapping for 0xf0000000 (MPCORE) */
21 .virtual = 0xf0000000,
22 .pfn = __phys_to_pfn(0xf0000000),
26 /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
28 .virtual = 0xfe000000,
29 .pfn = __phys_to_pfn(0xfe000000),
42 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
43 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
44 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
45 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/
H A Ddma.h19 #define B43_DMA32_TXCTL 0x00
20 #define B43_DMA32_TXENABLE 0x00000001
21 #define B43_DMA32_TXSUSPEND 0x00000002
22 #define B43_DMA32_TXLOOPBACK 0x00000004
23 #define B43_DMA32_TXFLUSH 0x00000010
24 #define B43_DMA32_TXPARITYDISABLE 0x00000800
25 #define B43_DMA32_TXADDREXT_MASK 0x00030000
27 #define B43_DMA32_TXRING 0x04
28 #define B43_DMA32_TXINDEX 0x08
29 #define B43_DMA32_TXSTATUS 0x0C
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A DMPC8349EMDS.h24 #define CONFIG_SYS_TEXT_BASE 0xFE000000
47 #define CONFIG_SYS_IMMR 0xE0000000
50 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
51 #define CONFIG_SYS_MEMTEST_END 0x00100000
64 #define CONFIG_SYS_SPD_BUS_NUM 0
65 #define SPD_EEPROM_ADDRESS1 0x52
66 #define SPD_EEPROM_ADDRESS2 0x51
70 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
84 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
94 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
/OK3568_Linux_fs/kernel/arch/arc/boot/dts/
H A Dnsim_700.dts17 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signal…
33 #clock-cells = <0>;
46 reg = <0xf0000000 0x2000>;
H A Dhaps_hs_idu.dts18 reg = <0x80000000 0x20000000>; /* 512 */
22 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-…
38 #clock-cells = <0>;
58 reg = <0xf0000000 0x2000>;
60 interrupts = <0>;
/OK3568_Linux_fs/kernel/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/OK3568_Linux_fs/kernel/arch/xtensa/include/asm/
H A Dkmem_layout.h23 #define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000)
24 #define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000)
28 #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
29 #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
30 #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
31 #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000)
37 #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000)
38 #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
39 #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000)
40 #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
[all …]
/OK3568_Linux_fs/u-boot/board/xes/xpedite537x/
H A Dxpedite537x.c37 set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); in flash_cs_fixup()
38 set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); in flash_cs_fixup()
48 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); in board_early_init_r()
49 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); in board_early_init_r()
50 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); in board_early_init_r()
51 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); in board_early_init_r()
63 disable_tlb(0); in board_early_init_r()
64 set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
65 (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
67 0, 0, BOOKE_PAGESZ_256M, 1); in board_early_init_r()
[all …]
/OK3568_Linux_fs/u-boot/board/xes/xpedite550x/
H A Dxpedite550x.c37 set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); in flash_cs_fixup()
38 set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); in flash_cs_fixup()
48 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); in board_early_init_r()
49 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); in board_early_init_r()
50 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); in board_early_init_r()
51 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); in board_early_init_r()
63 disable_tlb(0); in board_early_init_r()
64 set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
65 (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
67 0, 0, BOOKE_PAGESZ_256M, 1); in board_early_init_r()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Darmada-xp-gp.dts13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
17 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
41 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
45 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
46 <0x00000001 0x00000000 0x00000001 0x00000000>;
58 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
59 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
60 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
[all …]
/OK3568_Linux_fs/u-boot/board/xes/xpedite520x/
H A Dxpedite520x.c37 set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); in flash_cs_fixup()
38 set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); in flash_cs_fixup()
48 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); in board_early_init_r()
49 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); in board_early_init_r()
61 disable_tlb(0); in board_early_init_r()
62 set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
63 (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
65 0, 0, BOOKE_PAGESZ_256M, 1); in board_early_init_r()
69 return 0; in board_early_init_r()
80 return 0; in ft_board_setup()
/OK3568_Linux_fs/kernel/arch/sparc/lib/
H A Dfls.S16 mov 0, %o1
17 sethi %hi(0xffff0000), %g3
22 sethi %hi(0xff000000), %g3
25 sethi %hi(0xf0000000), %g3
29 sra %o0, 0, %o0
32 sethi %hi(0xf0000000), %g3
36 sethi %hi(0xc0000000), %g3
39 sra %o0, 0, %o0
51 sra %o1, 0, %o0
55 sra %o0, 0, %o0
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt24 0 <physical address of mapping> <size>
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
53 ALE[0] to the cycle that the first read data is sampled
63 DEV_OEn assertion. If set to 0 (default),
72 de-assertion of DEV_CSn. If set to 0 (default),
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
90 A[2:0] and Data are kept valid as long as DEV_WEn
97 DEV_A[2:0] and Data are kept valid (do not toggle) for
105 0: False
115 will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/phydm/
H A Dphydm_primary_cca.c47 odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC); in phydm_write_dynamic_cca()
49 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, in phydm_write_dynamic_cca()
52 odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state); in phydm_write_dynamic_cca()
54 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0); in phydm_write_dynamic_cca()
59 PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n", in phydm_write_dynamic_cca()
71 pri_cca->mf_state = 0xff; in phydm_primary_cca_reset()
72 pri_cca->pre_bw = (enum channel_width)0xff; in phydm_primary_cca_reset()
146 pri_cca->dup_rts_flag = 0; in phydm_primary_cca_init()
147 pri_cca->intf_flag = 0; in phydm_primary_cca_init()
148 pri_cca->intf_type = 0; in phydm_primary_cca_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/hal/phydm/
H A Dphydm_primary_cca.c48 odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC); in phydm_write_dynamic_cca()
50 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, in phydm_write_dynamic_cca()
53 odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state); in phydm_write_dynamic_cca()
55 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0); in phydm_write_dynamic_cca()
60 PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n", in phydm_write_dynamic_cca()
72 pri_cca->mf_state = 0xff; in phydm_primary_cca_reset()
73 pri_cca->pre_bw = (enum channel_width)0xff; in phydm_primary_cca_reset()
147 pri_cca->dup_rts_flag = 0; in phydm_primary_cca_init()
148 pri_cca->intf_flag = 0; in phydm_primary_cca_init()
149 pri_cca->intf_type = 0; in phydm_primary_cca_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/hal/phydm/
H A Dphydm_primary_cca.c48 odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC); in phydm_write_dynamic_cca()
50 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, in phydm_write_dynamic_cca()
53 odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state); in phydm_write_dynamic_cca()
55 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0); in phydm_write_dynamic_cca()
60 PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n", in phydm_write_dynamic_cca()
72 pri_cca->mf_state = 0xff; in phydm_primary_cca_reset()
73 pri_cca->pre_bw = (enum channel_width)0xff; in phydm_primary_cca_reset()
147 pri_cca->dup_rts_flag = 0; in phydm_primary_cca_init()
148 pri_cca->intf_flag = 0; in phydm_primary_cca_init()
149 pri_cca->intf_type = 0; in phydm_primary_cca_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/
H A Dphydm_primary_cca.c47 odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC); in phydm_write_dynamic_cca()
49 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, in phydm_write_dynamic_cca()
52 odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state); in phydm_write_dynamic_cca()
54 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0); in phydm_write_dynamic_cca()
59 PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n", in phydm_write_dynamic_cca()
71 pri_cca->mf_state = 0xff; in phydm_primary_cca_reset()
72 pri_cca->pre_bw = (enum channel_width)0xff; in phydm_primary_cca_reset()
146 pri_cca->dup_rts_flag = 0; in phydm_primary_cca_init()
147 pri_cca->intf_flag = 0; in phydm_primary_cca_init()
148 pri_cca->intf_type = 0; in phydm_primary_cca_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/hal/phydm/
H A Dphydm_primary_cca.c48 odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC); in phydm_write_dynamic_cca()
50 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, in phydm_write_dynamic_cca()
53 odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state); in phydm_write_dynamic_cca()
55 odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0); in phydm_write_dynamic_cca()
60 PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n", in phydm_write_dynamic_cca()
72 pri_cca->mf_state = 0xff; in phydm_primary_cca_reset()
73 pri_cca->pre_bw = (enum channel_width)0xff; in phydm_primary_cca_reset()
147 pri_cca->dup_rts_flag = 0; in phydm_primary_cca_init()
148 pri_cca->intf_flag = 0; in phydm_primary_cca_init()
149 pri_cca->intf_type = 0; in phydm_primary_cca_init()
[all …]

12345678910>>...41