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/OK3568_Linux_fs/u-boot/arch/arm/mach-rmobile/include/mach/
H A Dr8a7794.h15 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
18 #define MSTP0_BITS 0x00440801
19 #define MSTP1_BITS 0x936899DA
20 #define MSTP2_BITS 0x100D21FC
21 #define MSTP3_BITS 0xE084D810
22 #define MSTP4_BITS 0x800001C4
23 #define MSTP5_BITS 0x40C00044
24 #define MSTP7_BITS 0x013FE618
25 #define MSTP8_BITS 0x40803C05
26 #define MSTP9_BITS 0xFB879FEE
[all …]
H A Dr8a7795.h16 #define MSTP0_BITS 0x00640800
17 #define MSTP1_BITS 0xF3EE9390
18 #define MSTP2_BITS 0x340FAFDC
19 #define MSTP3_BITS 0xD80C7CDF
20 #define MSTP4_BITS 0x80000184
21 #define MSTP5_BITS 0x40BFFF46
22 #define MSTP6_BITS 0xE5FBEECF
23 #define MSTP7_BITS 0x39FFFF0E
24 #define MSTP8_BITS 0x01F19FF4
25 #define MSTP9_BITS 0xFFDFFFFF
[all …]
H A Dr8a7796.h16 #define MSTP0_BITS 0x00200000
17 #define MSTP1_BITS 0xFFFFFFFF
18 #define MSTP2_BITS 0x340E2FDC
19 #define MSTP3_BITS 0xFFFFFFDF
20 #define MSTP4_BITS 0x80000184
21 #define MSTP5_BITS 0xC3FFFFFF
22 #define MSTP6_BITS 0xFFFFFFFF
23 #define MSTP7_BITS 0xFFFFFFFF
24 #define MSTP8_BITS 0x01F1FFF7
25 #define MSTP9_BITS 0xFFFFFFFE
[all …]
H A Dr8a7790.h15 #define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
16 #define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
19 #define MSTP0_BITS 0x00640801
20 #define MSTP1_BITS 0xDB6E9BDF
21 #define MSTP2_BITS 0x300DA1FC
22 #define MSTP3_BITS 0xF08CF831
23 #define MSTP4_BITS 0x80000184
24 #define MSTP5_BITS 0x44C00046
25 #define MSTP7_BITS 0x07F30718
26 #define MSTP8_BITS 0x01F0FF84
[all …]
H A Dr8a7791.h18 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
21 #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
22 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
25 #define DBSC3_1_QOS_R0_BASE 0xE67A1000
26 #define DBSC3_1_QOS_R1_BASE 0xE67A1100
27 #define DBSC3_1_QOS_R2_BASE 0xE67A1200
28 #define DBSC3_1_QOS_R3_BASE 0xE67A1300
29 #define DBSC3_1_QOS_R4_BASE 0xE67A1400
30 #define DBSC3_1_QOS_R5_BASE 0xE67A1500
31 #define DBSC3_1_QOS_R6_BASE 0xE67A1600
[all …]
H A Dr8a7793.h19 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
22 #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
23 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
26 #define DBSC3_1_QOS_R0_BASE 0xE67A1000
27 #define DBSC3_1_QOS_R1_BASE 0xE67A1100
28 #define DBSC3_1_QOS_R2_BASE 0xE67A1200
29 #define DBSC3_1_QOS_R3_BASE 0xE67A1300
30 #define DBSC3_1_QOS_R4_BASE 0xE67A1400
31 #define DBSC3_1_QOS_R5_BASE 0xE67A1500
32 #define DBSC3_1_QOS_R6_BASE 0xE67A1600
[all …]
H A Drcar-gen3-base.h15 #define RWDT_BASE 0xE6020000
16 #define SWDT_BASE 0xE6030000
17 #define LBSC_BASE 0xEE220200
18 #define TMU_BASE 0xE61E0000
19 #define GPIO5_BASE 0xE6055000
22 #define SCIF0_BASE 0xE6E60000
23 #define SCIF1_BASE 0xE6E68000
24 #define SCIF2_BASE 0xE6E88000
25 #define SCIF3_BASE 0xE6C50000
26 #define SCIF4_BASE 0xE6C40000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Drenesas,sdhi.yaml100 pinctrl-0:
148 reg = <0xee100000 0x328>;
151 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
160 reg = <0xee120000 0x328>;
163 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
172 reg = <0xee140000 0x100>;
175 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
184 reg = <0xee160000 0x100>;
187 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dr8a7796.dtsi38 #size-cells = <0>;
40 a57_0: cpu@0 {
42 reg = <0x0>;
51 reg = <0x1>;
60 reg = <0x100>;
69 reg = <0x101>;
78 reg = <0x102>;
87 reg = <0x103>;
94 L2_CA57: cache-controller-0 {
111 #clock-cells = <0>;
[all …]
H A Dr8a7795.dtsi38 #size-cells = <0>;
40 a57_0: cpu@0 {
42 reg = <0x0>;
51 reg = <0x1>;
60 reg = <0x2>;
69 reg = <0x3>;
78 reg = <0x100>;
87 reg = <0x101>;
96 reg = <0x102>;
105 reg = <0x103>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dr8a77470.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0>;
50 L2_CA7: cache-controller-0 {
61 #clock-cells = <0>;
63 clock-frequency = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
92 reg = <0 0xe6020000 0 0x0c>;
102 reg = <0 0xe6050000 0 0x50>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7745.dtsi36 * The external audio clocks are configured as 0 Hz fixed
42 #clock-cells = <0>;
43 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #size-cells = <0>;
[all …]
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/renesas/
H A Dr8a774c0.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a77990.dtsi29 * The external audio clocks are configured as 0 Hz fixed frequency
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
81 #size-cells = <0>;
[all …]
H A Dr8a77961.dtsi20 * The external audio clocks are configured as 0 Hz fixed frequency
26 #clock-cells = <0>;
27 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
118 #size-cells = <0>;
[all …]
H A Dr8a774a1.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
106 #size-cells = <0>;
[all …]
H A Dr8a774b1.dtsi21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
74 #size-cells = <0>;
[all …]
H A Dr8a77965.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
105 #size-cells = <0>;
[all …]

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