Searched +full:0 +full:xe6150000 (Results 1 – 25 of 32) sorted by relevance
12
19 #size-cells = <0>;21 a76_0: cpu@0 {23 reg = <0>;29 L3_CA76_0: cache-controller-0 {39 #clock-cells = <0>;41 clock-frequency = <0>;46 #clock-cells = <0>;48 clock-frequency = <0>;59 #clock-cells = <0>;60 clock-frequency = <0>;[all …]
21 #clock-cells = <0>;22 clock-frequency = <0>;27 #size-cells = <0>;29 a53_0: cpu@0 {31 reg = <0x0>;48 #clock-cells = <0>;50 clock-frequency = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;79 reg = <0 0xe6020000 0 0x0c>;[all …]
30 #clock-cells = <0>;31 clock-frequency = <0>;36 #size-cells = <0>;38 a53_0: cpu@0 {41 reg = <0>;68 #clock-cells = <0>;70 clock-frequency = <0>;75 #clock-cells = <0>;77 clock-frequency = <0>;95 #clock-cells = <0>;[all …]
31 #clock-cells = <0>;32 clock-frequency = <0>;37 #size-cells = <0>;39 a53_0: cpu@0 {42 reg = <0>;89 #clock-cells = <0>;91 clock-frequency = <0>;96 #clock-cells = <0>;98 clock-frequency = <0>;104 #clock-cells = <0>;[all …]
18 * The external audio clocks are configured as 0 Hz fixed frequency24 #clock-cells = <0>;25 clock-frequency = <0>;30 #clock-cells = <0>;31 clock-frequency = <0>;36 #clock-cells = <0>;37 clock-frequency = <0>;43 #clock-cells = <0>;44 clock-frequency = <0>;70 #size-cells = <0>;[all …]
29 * The external audio clocks are configured as 0 Hz fixed frequency35 #clock-cells = <0>;36 clock-frequency = <0>;41 #clock-cells = <0>;42 clock-frequency = <0>;47 #clock-cells = <0>;48 clock-frequency = <0>;54 #clock-cells = <0>;55 clock-frequency = <0>;81 #size-cells = <0>;[all …]
83 const: 0116 reg = <0xe6150000 0x1000>;120 #power-domain-cells = <0>;
45 minimum: 049 const: 0234 reg = <0xe6150000 0x10000>;240 renesas,mode = <0x05>;
14 #define MERAM_BASE 0xE558000015 #define DDRP_BASE 0xC12A000016 #define HPB_BASE 0xE600000017 #define RWDT0_BASE 0xE602000018 #define RWDT1_BASE 0xE603000019 #define GPIO_BASE 0xE605000020 #define CMT1_BASE 0xE613800021 #define CPG_BASE 0xE615000022 #define SYSC_BASE 0xE618000023 #define SDHI0_BASE 0xE6850000[all …]
5 #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)6 #define MERAM_BASE (0xE5580000)9 #define GIC_BASE (0xF0000100)13 #define LIFEC_SEC_SRC (0xE6110008)16 #define RWDT_BASE (0xE6020000)19 #define HPB_BASE (0xE6001010)22 #define HPBSCR_BASE (0xE6001600)25 #define SBSC1_BASE (0xFE400000)26 #define SDMRA1A (SBSC1_BASE + 0x100000)27 #define SDMRA2A (SBSC1_BASE + 0x1C0000)[all …]
20 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;35 reg = <0xc2800000 0x1000>,36 <0xc2000000 0x1000>;41 reg = <0xf0100000 0x1000>;53 reg = <0xfe400000 0x400>;68 reg = <0xfe910000 0x3000>;77 reg = <0xfe914000 0x3000>;87 reg = <0xe6138000 0x170>;[all …]
21 #size-cells = <0>;23 cpu0: cpu@0 {26 reg = <0>;33 L2_CA15: cache-controller-0 {65 reg = <0 0xe6790000 0 0x10000>;71 reg = <0 0xe67a0000 0 0x10000>;86 reg = <0 0xe6700020 0 0x89e0>;121 #size-cells = <0>;123 reg = <0 0xe60b0000 0 0x428>;133 reg = <0 0xe6130000 0 0x1004>;[all …]
40 #clock-cells = <0>;42 clock-frequency = <0>;47 #size-cells = <0>;50 cpu0: cpu@0 {53 reg = <0>;70 L2_CA15: cache-controller-0 {81 #clock-cells = <0>;83 clock-frequency = <0>;96 #clock-cells = <0>;98 clock-frequency = <0>;[all …]
20 #size-cells = <0>;22 cpu0: cpu@0 {25 reg = <0>;44 reg = <0xf0000200 0x100>;51 reg = <0xf0000600 0x20>;60 reg = <0xf0001000 0x1000>,61 <0xf0000100 0x100>;66 reg = <0xf0100000 0x1000>;78 reg = <0xfb400000 0x400>;87 reg = <0xfe400000 0x400>;[all …]
27 #size-cells = <0>;30 cpu0: cpu@0 {33 reg = <0>;50 L2_CA7: cache-controller-0 {61 #clock-cells = <0>;63 clock-frequency = <0>;76 #clock-cells = <0>;78 clock-frequency = <0>;92 reg = <0 0xe6020000 0 0x0c>;102 reg = <0 0xe6050000 0 0x50>;[all …]
34 * The external audio clocks are configured as 0 Hz fixed frequency40 #clock-cells = <0>;41 clock-frequency = <0>;45 #clock-cells = <0>;46 clock-frequency = <0>;50 #clock-cells = <0>;51 clock-frequency = <0>;57 #clock-cells = <0>;59 clock-frequency = <0>;64 #size-cells = <0>;[all …]
32 * The external audio clocks are configured as 0 Hz fixed frequency38 #clock-cells = <0>;39 clock-frequency = <0>;43 #clock-cells = <0>;44 clock-frequency = <0>;48 #clock-cells = <0>;49 clock-frequency = <0>;55 #clock-cells = <0>;57 clock-frequency = <0>;62 #size-cells = <0>;[all …]
36 * The external audio clocks are configured as 0 Hz fixed42 #clock-cells = <0>;43 clock-frequency = <0>;47 #clock-cells = <0>;48 clock-frequency = <0>;52 #clock-cells = <0>;53 clock-frequency = <0>;59 #clock-cells = <0>;61 clock-frequency = <0>;66 #size-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;30 #clock-cells = <0>;31 clock-frequency = <0>;35 #clock-cells = <0>;36 clock-frequency = <0>;42 #clock-cells = <0>;44 clock-frequency = <0>;49 #size-cells = <0>;[all …]
40 * The external audio clocks are configured as 0 Hz fixed frequency46 #clock-cells = <0>;47 clock-frequency = <0>;51 #clock-cells = <0>;52 clock-frequency = <0>;56 #clock-cells = <0>;57 clock-frequency = <0>;63 #clock-cells = <0>;65 clock-frequency = <0>;70 #size-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;31 #clock-cells = <0>;32 clock-frequency = <0>;37 #clock-cells = <0>;38 clock-frequency = <0>;44 #clock-cells = <0>;46 clock-frequency = <0>;51 #size-cells = <0>;[all …]
41 * The external audio clocks are configured as 0 Hz fixed frequency47 #clock-cells = <0>;48 clock-frequency = <0>;52 #clock-cells = <0>;53 clock-frequency = <0>;57 #clock-cells = <0>;58 clock-frequency = <0>;64 #clock-cells = <0>;66 clock-frequency = <0>;71 #size-cells = <0>;[all …]
38 #size-cells = <0>;40 a57_0: cpu@0 {42 reg = <0x0>;51 reg = <0x1>;60 reg = <0x100>;69 reg = <0x101>;78 reg = <0x102>;87 reg = <0x103>;94 L2_CA57: cache-controller-0 {111 #clock-cells = <0>;[all …]
38 #size-cells = <0>;40 a57_0: cpu@0 {42 reg = <0x0>;51 reg = <0x1>;60 reg = <0x2>;69 reg = <0x3>;78 reg = <0x100>;87 reg = <0x101>;96 reg = <0x102>;105 reg = <0x103>;[all …]