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Searched +full:0 +full:xe2800000 (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/staging/board/
H A Dkzm9d.c9 DEFINE_RES_MEM(0xe2800000, 0x2000),
/OK3568_Linux_fs/u-boot/include/configs/
H A D3c120_devboard.h35 #define CONFIG_SYS_RX_ETH_BUFFER 0
58 #define CONFIG_SYS_SDRAM_BASE 0xD0000000
59 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
62 #define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
66 #define CONFIG_SYS_MALLOC_LEN 0x20000
76 #define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
78 #define CONFIG_ENV_ADDR (0xe2800000 + CONFIG_SYS_MONITOR_LEN)
84 #define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */
90 0x10000)
H A DMPC8568MDS.h13 #define CONFIG_SYS_TEXT_BASE 0xfff80000
44 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
45 #define CONFIG_SYS_MEMTEST_END 0x00400000
47 #define CONFIG_SYS_CCSRBAR 0xe0000000
56 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
58 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
65 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
81 * Boot from BR0/OR0 bank at 0xff00_0000
82 * Alternate BR1/OR1 bank at 0xff80_0000
85 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
[all …]
H A DMPC8569MDS.h43 #define CONFIG_SYS_TEXT_BASE 0xfff80000
58 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
59 #define CONFIG_SYS_MEMTEST_END 0x00400000
64 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
69 #define CONFIG_SYS_CCSRBAR 0xe0000000
82 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
92 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
96 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
97 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
[all …]
H A Dsbc8548.h49 #define CONFIG_SYS_TEXT_BASE 0xfff00000
51 #define CONFIG_SYS_TEXT_BASE 0xfffa0000
90 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
91 #define CONFIG_SYS_MEMTEST_END 0x00400000
93 #define CONFIG_SYS_CCSRBAR 0xe0000000
105 * for a device at 0x53.
111 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
113 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
122 * SPD at 0x53, but if we are running on an older board w/o the
123 * fix, it will still be at 0x51. We check 0x53 1st.
[all …]
H A DMPC8313ERDB.h31 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
32 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
34 #define CONFIG_SPL_PAD_TO 0x4000
37 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
38 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
40 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
41 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
50 #define CONFIG_SYS_TEXT_BASE 0xFE000000
83 #define CONFIG_SYS_IMMR 0xE0000000
89 #define CONFIG_SYS_MEMTEST_START 0x00001000
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dmpc8548cds_32b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
23 0x1 0x0 0x0 0xf8004000 0x00001000>;
28 ranges = <0 0x0 0xe0000000 0x100000>;
32 reg = <0 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
39 reg = <0 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
[all …]
H A Dmpc8548cds_36b.dts16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
20 reg = <0xf 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0xf 0xff000000 0x01000000
23 0x1 0x0 0xf 0xf8004000 0x00001000>;
28 ranges = <0 0xf 0xe0000000 0x100000>;
32 reg = <0xf 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
34 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
39 reg = <0xf 0xe0009000 0 0x1000>;
40 ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
[all …]
H A Dmpc8568mds.dts22 reg = <0x0 0x0 0x0 0x0>;
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
33 nor@0,0 {
37 reg = <0x0 0x0 0x02000000>;
42 bcsr@1,0 {
[all …]
H A Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
39 nor@0,0 {
43 reg = <0x0 0x0 0x02000000>;
46 partition@0 {
[all …]
/OK3568_Linux_fs/u-boot/board/sbc8548/
H A Dtlb.c14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/OK3568_Linux_fs/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S24 mov r5, #0
29 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
30 orr r0, r0, #0x0
35 ldr r1, =0x9
39 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
40 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
41 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
44 mvn r3, #0x0
45 str r3, [r0, #0x14] @INTENCLEAR
46 str r3, [r1, #0x14] @INTENCLEAR
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dspear1340.dtsi17 reg = <0xe0700000 0x1000>;
18 st-spics,peripcfg-reg = <0x42c>;
30 reg = <0xeb800000 0x4000>;
38 reg = <0xb1000000 0x10000>;
39 interrupts = <0 72 0x4>;
40 phys = <&miphy0 0>;
47 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
49 interrupts = <0 68 0x4>;
50 interrupt-map-mask = <0 0 0 0>;
51 interrupt-map = <0x0 0 &gic 0 68 0x4>;
[all …]
H A Ds5pv210.dtsi46 #size-cells = <0>;
48 cpu@0 {
51 reg = <0>;
55 xxti: oscillator-0 {
57 clock-frequency = <0>;
59 #clock-cells = <0>;
64 clock-frequency = <0>;
66 #clock-cells = <0>;
77 reg = <0xb0600000 0x2000>,
78 <0xb0000000 0x20000>,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml129 enum: [0, 1]
150 enum: [0, 2]
151 default: 0
172 reg = <0xe0100000 0x1000>;
176 interrupts = <0 24 4>;
182 reg = <0xe2800000 0x1000>;
186 interrupts = <0 24 4>;
197 reg = <0xfe330000 0x10000>;
207 #clock-cells = <0>;
214 interrupts = <0 48 4>;
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dsbc8548-post.dtsi15 ranges = <0x00000000 0xe0000000 0x00100000>;
16 bus-frequency = <0>;
19 ecm-law@0 {
21 reg = <0x0 0x1000>;
27 reg = <0x1000 0x1000>;
34 reg = <0x2000 0x1000>;
36 interrupts = <0x12 0x2>;
41 reg = <0x20000 0x1000>;
42 cache-line-size = <0x20>; // 32 bytes
43 cache-size = <0x80000>; // L2, 512K
[all …]
H A Dmpc8313erdb.dts26 #size-cells = <0>;
28 PowerPC,8313@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]