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/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/
H A Dda830.c31 #define DA830_CMP12_0 0x60
32 #define DA830_CMP12_1 0x64
33 #define DA830_CMP12_2 0x68
34 #define DA830_CMP12_3 0x6c
35 #define DA830_CMP12_4 0x70
36 #define DA830_CMP12_5 0x74
37 #define DA830_CMP12_6 0x78
38 #define DA830_CMP12_7 0x7c
50 MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false)
51 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
[all …]
/OK3568_Linux_fs/kernel/sound/soc/fsl/
H A Dfsl_asrc.c46 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
52 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
59 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
60 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
61 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
62 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
66 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
67 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
68 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
69 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/
H A Dmac_reg.h28 #define R_AX_GT0_CTRL 0x8000
33 #define B_AX_GT0_DATA_SH 0
34 #define B_AX_GT0_DATA_MSK 0xfffffff
36 #define R_AX_GT0_CNT 0x8004
37 #define B_AX_GT0_CNT_SH 0
38 #define B_AX_GT0_CNT_MSK 0x1fffffff
40 #define R_AX_GT1_CTRL 0x8008
45 #define B_AX_GT1_DATA_SH 0
46 #define B_AX_GT1_DATA_MSK 0xfffffff
48 #define R_AX_GT1_CNT 0x800C
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/
H A Dmac_reg.h28 #define R_AX_GT0_CTRL 0x8000
33 #define B_AX_GT0_DATA_SH 0
34 #define B_AX_GT0_DATA_MSK 0xfffffff
36 #define R_AX_GT0_CNT 0x8004
37 #define B_AX_GT0_CNT_SH 0
38 #define B_AX_GT0_CNT_MSK 0x1fffffff
40 #define R_AX_GT1_CTRL 0x8008
45 #define B_AX_GT1_DATA_SH 0
46 #define B_AX_GT1_DATA_MSK 0xfffffff
48 #define R_AX_GT1_CNT 0x800C
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dcyrus_p5020.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dmpc8572ds_36b.dts19 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
22 0x1 0x0 0xf 0xe0000000 0x08000000
23 0x2 0x0 0xf 0xffa00000 0x00040000
24 0x3 0x0 0xf 0xffdf0000 0x00008000
25 0x4 0x0 0xf 0xffa40000 0x00040000
26 0x5 0x0 0xf 0xffa80000 0x00040000
27 0x6 0x0 0xf 0xffac0000 0x00040000>;
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
35 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dkmcent2.dts27 size = <0 0x1000000>;
28 alignment = <0 0x1000000>;
31 size = <0 0x400000>;
32 alignment = <0 0x400000>;
35 size = <0 0x2000000>;
36 alignment = <0 0x2000000>;
41 reg = <0xf 0xfe124000 0 0x2000>;
42 ranges = <0 0 0xf 0xe8000000 0x04000000
43 1 0 0xf 0xfa000000 0x00010000
44 2 0 0xf 0xfb000000 0x00010000
[all …]
H A Dmpc8536ds_36b.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0xf 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
35 0x2 0x0 0xf 0xffa00000 0x00040000
36 0x3 0x0 0xf 0xffdf0000 0x00008000>;
40 ranges = <0x0 0xf 0xffe00000 0x100000>;
44 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dt104xd4rdb.dtsi42 size = <0 0x1000000>;
43 alignment = <0 0x1000000>;
46 size = <0 0x400000>;
47 alignment = <0 0x400000>;
50 size = <0 0x2000000>;
51 alignment = <0 0x2000000>;
56 reg = <0xf 0xfe124000 0 0x2000>;
57 ranges = <0 0 0xf 0xe8000000 0x08000000
58 2 0 0xf 0xff800000 0x00010000
59 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dt104xrdb.dtsi48 size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
H A Dt208xrdb.dtsi48 size = <0 0x1000000>;
49 alignment = <0 0x1000000>;
52 size = <0 0x400000>;
53 alignment = <0 0x400000>;
56 size = <0 0x2000000>;
57 alignment = <0 0x2000000>;
62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0x00008000>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dclock.c33 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
34 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
35 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
36 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
37 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
38 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
39 {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
40 {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
41 {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
42 {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dar9003_aic.c25 0, 3, 9, 15, 21, 27
67 for (i = index - 1; i >= 0; i--) { in ar9003_aic_find_valid()
73 if ((i >= ATH_AIC_MAX_BT_CHANNEL) || (i < 0)) in ar9003_aic_find_valid()
80 * type 0: aic_lin_table, 1: com_att_db_table
86 if (type == 0) { in ar9003_aic_find_index()
87 for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { in ar9003_aic_find_index()
92 for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) { in ar9003_aic_find_index()
111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); in ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); in ar9003_aic_gain_table()
115 aic_atten_word[0] = (0x1 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/mediatek/mt8183/
H A Dmt8183-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/fw_ax/inc_hdr/
H A Dfwcmd_intf.h4 #define FWCMD_VER 0x0
11 #define FWCMD_H2CREG_FUNC_H2CREG_LB 0x0
12 #define FWCMD_H2CREG_FUNC_CNSL_CMD 0x1
13 #define FWCMD_H2CREG_FUNC_FWERR 0x2
14 #define FWCMD_H2CREG_FUNC_HIDDEN_GET 0x3
15 #define FWCMD_H2CREG_FUNC_GETPKT_INFORM 0x4
16 #define FWCMD_H2CREG_FUNC_SCH_TX_EN 0x5
17 #define FWCMD_H2CREG_FUNC_WOW_TRX_STOP 0x6
18 #define FWCMD_H2CREG_FUNC_AOAC_RPT_1 0x7
19 #define FWCMD_H2CREG_FUNC_AOAC_RPT_2 0x8
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/fw_ax/inc_hdr/
H A Dfwcmd_intf.h4 #define FWCMD_VER 0x0
11 #define FWCMD_H2CREG_FUNC_H2CREG_LB 0x0
12 #define FWCMD_H2CREG_FUNC_CNSL_CMD 0x1
13 #define FWCMD_H2CREG_FUNC_FWERR 0x2
14 #define FWCMD_H2CREG_FUNC_HIDDEN_GET 0x3
15 #define FWCMD_H2CREG_FUNC_GETPKT_INFORM 0x4
16 #define FWCMD_H2CREG_FUNC_SCH_TX_EN 0x5
17 #define FWCMD_H2CREG_FUNC_WOW_TRX_STOP 0x6
18 #define FWCMD_H2CREG_FUNC_AOAC_RPT_1 0x7
19 #define FWCMD_H2CREG_FUNC_AOAC_RPT_2 0x8
[all …]
/OK3568_Linux_fs/buildroot/board/forlinx/ok3568/fs-overlay/usr/lib/firmware/nxp/
H A Dwifi_mod_para.conf19 # specify the configuration block id number [0 - 9], if not
20 # specified, it is taken as 0 by default.
31 cfg80211_wext=0xf
41 # cfg80211_wext=0xf
49 # cfg80211_wext=0xf
57 # cfg80211_wext=0xf
65 # cfg80211_wext=0xf
73 cfg80211_wext=0xf
84 # cfg80211_wext=0xf
91 cfg80211_wext=0xf
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8173.c9 #define HDMI_CON0 0x00
11 #define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
13 #define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
15 #define RG_HDMITX_PLL_PREDIV (0x3 << 20)
17 #define RG_HDMITX_PLL_POSDIV (0x3 << 18)
19 #define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
20 #define RG_HDMITX_PLL_IR (0xf << 12)
22 #define RG_HDMITX_PLL_IC (0xf << 8)
24 #define RG_HDMITX_PLL_BP (0xf << 4)
26 #define RG_HDMITX_PLL_BR (0x3 << 2)
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/gaudi/
H A Dgaudi_masks.h15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/tegra/
H A Dsor.h9 #define SOR_CTXSW 0x00
11 #define SOR_SUPER_STATE0 0x01
13 #define SOR_SUPER_STATE1 0x02
16 #define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0)
17 #define SOR_SUPER_STATE_HEAD_MODE_AWAKE (2 << 0)
18 #define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0)
19 #define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0)
21 #define SOR_STATE0 0x03
23 #define SOR_STATE1 0x04
24 #define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/amd/
H A Damd8111e.h20 3.0.0
32 … 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits w…
39 #define ASF_STAT 0x00 /* ASF status register */
40 #define CHIPID 0x04 /* Chip ID register */
41 #define MIB_DATA 0x10 /* MIB data register */
42 #define MIB_ADDR 0x14 /* MIB address register */
43 #define STAT0 0x30 /* Status0 register */
44 #define INT0 0x38 /* Interrupt0 register */
45 #define INTEN0 0x40 /* Interrupt0 enable register*/
46 #define CMD0 0x48 /* Command0 register */
[all …]
/OK3568_Linux_fs/kernel/arch/sh/boards/mach-sh03/
H A Drtc.c20 #define RTC_BASE 0xb0000000
21 #define RTC_SEC1 (RTC_BASE + 0)
49 sec = (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10; in sh03_rtc_gettimeofday()
50 min = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10; in sh03_rtc_gettimeofday()
51 hour = (__raw_readb(RTC_HOU1) & 0xf) + (__raw_readb(RTC_HOU10) & 0xf) * 10; in sh03_rtc_gettimeofday()
52 day = (__raw_readb(RTC_DAY1) & 0xf) + (__raw_readb(RTC_DAY10) & 0xf) * 10; in sh03_rtc_gettimeofday()
53 mon = (__raw_readb(RTC_MON1) & 0xf) + (__raw_readb(RTC_MON10) & 0xf) * 10; in sh03_rtc_gettimeofday()
54 year = (__raw_readb(RTC_YEA1) & 0xf) + (__raw_readb(RTC_YEA10) & 0xf) * 10 in sh03_rtc_gettimeofday()
55 + (__raw_readb(RTC_YEA100 ) & 0xf) * 100 in sh03_rtc_gettimeofday()
56 + (__raw_readb(RTC_YEA1000) & 0xf) * 1000; in sh03_rtc_gettimeofday()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c61 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
63 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
65 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0, in mpc1_set_bg_color()
149 if (top_sel == 0xf && opp_id == 0xf && idle) in mpc1_is_mpcc_idle()
163 if (top_sel == 0xf) { in mpc1_assert_mpcc_idle_before_connect()
168 ASSERT(mpc_busy == 0); in mpc1_assert_mpcc_idle_before_connect()
222 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); in mpc1_insert_plane()
226 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
229 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); in mpc1_insert_plane()
230 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
/OK3568_Linux_fs/kernel/drivers/ssb/
H A Ddriver_chipcommon_pmu.c52 u8 xf; /* Crystal frequency value for PMU control */ member
58 { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
59 { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
60 { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
61 { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
62 { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
63 { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
64 { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
65 { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
66 { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
[all …]

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