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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dopenbmc-flash-layout-128.dtsi8 u-boot@0 {
9 reg = <0x0 0xe0000>; // 896KB
14 reg = <0xe0000 0x20000>; // 128KB
19 reg = <0x100000 0x900000>; // 9MB
24 reg = <0xa00000 0x5600000>; // 86MB
29 reg = <0x6000000 0x2000000>; // 32MB
H A Darmada-385-linksys-shelby.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Darmada-385-linksys-caiman.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Darmada-385-linksys-cobra.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Dpm9g45.dts19 reg = <0x70000000 0x8000000>;
40 pinctrl_nand_rb: nand-rb-0 {
55 timer@0 {
57 reg = <0>, <1>;
67 pinctrl-0 = <
73 slot@0 {
74 reg = <0>;
91 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
95 reg = <0x3 0x0 0x800000>;
108 at91bootstrap@0 {
[all …]
H A Daspeed-ast2600-evb.dts22 reg = <0x80000000 0x80000000>;
29 ethphy1: ethernet-phy@0 {
31 reg = <0>;
38 ethphy2: ethernet-phy@0 {
40 reg = <0>;
47 ethphy3: ethernet-phy@0 {
49 reg = <0>;
60 pinctrl-0 = <&pinctrl_rgmii2_default>;
70 pinctrl-0 = <&pinctrl_rgmii3_default>;
80 pinctrl-0 = <&pinctrl_rgmii4_default>;
[all …]
H A Dox810se.dtsi17 #address-cells = <0>;
18 #size-cells = <0>;
29 /* Max 256MB @ 0x48000000 */
30 reg = <0x48000000 0x10000000>;
36 #clock-cells = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
62 #clock-cells = <0>;
70 #clock-cells = <0>;
[all …]
H A Darmada-xp-linksys-mamba.dts6 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
34 memory@0 {
36 reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
64 pinctrl-0 = <&ge0_rgmii_pins>;
69 bm,pool-long = <0>;
[all …]
H A Dqcom-msm8960.dtsi18 #size-cells = <0>;
19 interrupts = <1 14 0x304>;
21 cpu@0 {
25 reg = <0>;
49 reg = <0x0 0x0>;
54 interrupts = <1 10 0x304>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
91 reg = <0x02000000 0x1000>,
[all …]
H A Dqcom-mdm9615.dtsi63 #size-cells = <0>;
65 cpu0: cpu@0 {
80 #clock-cells = <0>;
103 reg = <0x02040000 0x1000>;
104 arm,data-latency = <2 2 0>;
113 reg = <0x02000000 0x1000>,
114 <0x02002000 0x1000>;
122 reg = <0x0200a000 0x100>;
125 cpu-offset = <0x80000>;
131 gpio-ranges = <&msmgpio 0 0 88>;
[all …]
H A Dqcom-msm8660.dtsi18 #size-cells = <0>;
20 cpu@0 {
24 reg = <0>;
44 reg = <0x0 0x0>;
49 interrupts = <1 9 0x304>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
79 io-channels = <&xoadc 0x00 0x01>, /* Battery */
80 <&xoadc 0x00 0x02>, /* DC in (charger) */
[all …]
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/include/asm/
H A Dunistd.h17 #define __NR_OABI_SYSCALL_BASE 0x900000
20 #define __NR_SYSCALL_BASE 0
33 #define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000)
/OK3568_Linux_fs/kernel/arch/arm/include/uapi/asm/
H A Dunistd.h17 #define __NR_OABI_SYSCALL_BASE 0x900000
20 #define __NR_SYSCALL_BASE 0
33 #define __ARM_NR_BASE (__NR_SYSCALL_BASE+0x0f0000)
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Doxnas,pinctrl.txt45 reg = <0x900000 0x100000>;
48 reg-shift = <0>;
55 pinctrl-0 = <&pinctrl_uart2>;
/OK3568_Linux_fs/u-boot/doc/uImage.FIT/
H A Dhowto.txt89 Image 0 (kernel@1)
96 Load Address: 0x00000000
97 Entry Point: 0x00000000
103 Configuration 0 (config@1)
123 Load address: 0x900000
133 Image 0 (kernel@1)
137 Data Start: 0x009000e0
141 Load Address: 0x00000000
142 Entry Point: 0x00000000
148 Configuration 0 (config@1)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc.yaml87 reg = <0x900000 0x4000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.txt12 0 - USB3
16 0 - PCIe1 Lane0
62 reg = <0x0 0x900000 0x0 0x2000>;
73 mux-controls = <&serdes_mux 0>;
/OK3568_Linux_fs/kernel/sound/drivers/vx/
H A Dvx_cmd.c19 [CMD_VERSION] = { 0x010000, 2, RMH_SSIZE_FIXED, 1 },
20 [CMD_SUPPORTED] = { 0x020000, 1, RMH_SSIZE_FIXED, 2 },
21 [CMD_TEST_IT] = { 0x040000, 1, RMH_SSIZE_FIXED, 1 },
22 [CMD_SEND_IRQA] = { 0x070001, 1, RMH_SSIZE_FIXED, 0 },
23 [CMD_IBL] = { 0x080000, 1, RMH_SSIZE_FIXED, 4 },
24 [CMD_ASYNC] = { 0x0A0000, 1, RMH_SSIZE_ARG, 0 },
25 [CMD_RES_PIPE] = { 0x400000, 1, RMH_SSIZE_FIXED, 0 },
26 [CMD_FREE_PIPE] = { 0x410000, 1, RMH_SSIZE_FIXED, 0 },
27 [CMD_CONF_PIPE] = { 0x42A101, 2, RMH_SSIZE_FIXED, 0 },
28 [CMD_ABORT_CONF_PIPE] = { 0x42A100, 2, RMH_SSIZE_FIXED, 0 },
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dconfig.h13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
32 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
33 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
34 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
49 #define GICD_BASE 0x06000000
50 #define GICR_BASE 0x06100000
53 #define SMMU_BASE 0x05000000 /* GR0 Base */
70 #define CCI_MN_BASE 0x04000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-rockchip/
H A Drv1106_pm.h9 #define RV1106_WAKEUP_TO_SYSTEM_RESET 0
11 #define RV1106_PERIGRF_OFFSET 0x0
12 #define RV1106_VENCGRF_OFFSET 0x10000
13 #define RV1106_NPUGRF_OFFSET 0x18000
14 #define RV1106_PMUGRF_OFFSET 0x20000
15 #define RV1106_DDRGRF_OFFSET 0x30000
16 #define RV1106_COREGRF_OFFSET 0x40000
17 #define RV1106_VIGRF_OFFSET 0x50000
18 #define RV1106_VOGRF_OFFSET 0x60000
20 #define RV1106_PERISGRF_OFFSET 0x70000
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dls1043a_common.h38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
71 #define CONFIG_SPL_TEXT_BASE 0x10000000
72 #define CONFIG_SPL_MAX_SIZE 0x17000
73 #define CONFIG_SPL_STACK 0x1001e000
74 #define CONFIG_SPL_PAD_TO 0x1d000
78 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
79 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/wil6210/
H A Dwmi.c21 int agg_wsize; /* = 0; */
24 " 0 - use default; < 0 - don't auto-establish");
29 " 60G device led enablement. Set the led ID (0-2) to enable");
62 * AHB addresses starting from 0x880000
75 * 0x880000 .. 0xa80000 2Mb BAR0
76 * 0x800000 .. 0x808000 0x900000 .. 0x908000 32k DCCM
77 * 0x840000 .. 0x860000 0x908000 .. 0x928000 128k PERIPH
81 {0x000000, 0x040000, 0x8c0000, "fw_code", true, true},
83 {0x800000, 0x808000, 0x900000, "fw_data", true, true},
85 {0x840000, 0x860000, 0x908000, "fw_peri", true, true},
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/controller/
H A Dpcie-rockchip.h29 #define PCIE_CLIENT_BASE 0x0
30 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
31 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
32 #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
33 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
34 #define PCIE_CLIENT_LINK_TRAIN_DISABLE HIWORD_UPDATE(0x0002, 0x0000)
35 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
36 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
37 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
38 #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h25 #define EP93XX_AHB_BASE 0x80000000
26 #define EP93XX_APB_BASE 0x80800000
29 * 0x80000000 - 0x8000FFFF: DMA
31 #define DMA_OFFSET 0x000000
74 * 0x80010000 - 0x8001FFFF: Ethernet MAC
76 #define MAC_OFFSET 0x010000
156 #define SELFCTL_RESET (1 << 0)
187 #define BMCTL_RXEN (1 << 0)
192 #define BMSTS_QID_MASK 0x07
193 #define BMSTS_QID_RXDATA 0x00
[all …]

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